System and Method for Independent, Direct and Parallel Communication Among Multiple Field Programmable Gate Arrays

Abstract

Representative embodiments are disclosed for data transfer between field programmable gate arrays (FPGAs). A representative system includes: a PCIe communication network comprising a PCIe switch and a plurality of PCIe communication lines; a host computing system coupled to the PCIe communication network; a nonblocking crossbar switch; a plurality of memory circuits; and a plurality of field programmable gate arrays, each field programmable gate array configurable for a plurality of data transfers to and from the host computing system and any other field programmable gate array of the plurality of field programmable gate arrays, with each data transfer including a designation of a first memory address, a file size, and a stream number. Once base DMA registers have been initialized for a selected application, no further involvement by the host computing system is involved for the duration of the selected application.

It is claimed: 
     
         1 . A computing system, the computing system comprising:
 a PCIe communication network comprising a PCIe switch and a plurality of PCIe communication lines;   a plurality of memory circuits; and   a plurality of configurable logic circuits, each configurable logic circuit of the plurality of configurable logic circuits coupled to the PCIe communication network and to at least one memory circuit of the plurality of memory circuits, each configurable logic circuit, of the plurality of configurable logic circuits, configured to generate a data packet for each data transfer of a plurality of data transfers, the data packet comprising a data transfer header having a designation of a first memory address and a stream number.   
     
     
         2 . The computing system of  claim 1 , wherein each configurable logic circuit of the plurality of configurable logic circuits is further configured to generate a plurality of data transfers to any other configurable logic circuit of the plurality of configurable logic circuits. 
     
     
         3 . The computing system of  claim 1 , further comprising:
 at least one field programmable gate array configured as a non-blocking crossbar switch and coupled to the configurable logic circuits;   wherein each configurable logic circuit of the plurality of configurable logic circuits is further configured to perform one or more data transfers through the PCIe communication network or through the nonblocking crossbar switch, and wherein each configurable logic circuit of the plurality of configurable logic circuits is further configured to perform at least some data transfers of the plurality of data transfers in parallel and directly between or among the plurality of configurable logic circuits.   
     
     
         4 . The computing system of  claim 1 , wherein each configurable logic circuit of the plurality of configurable logic circuits is further configured to include a file size designation in the data transfer header. 
     
     
         5 . The computing system of  claim 1 , wherein the computing system further comprises one or more processor circuits, and wherein prior to commencement of a computing application to be performed by one or more configurable logic circuits of the plurality of configurable logic circuits, the one or more processor circuits are adapted to transmit a plurality of DMA register messages to the configurable logic circuits of the plurality of configurable logic circuits, each DMA register message having a plurality of designations comprising a memory address of the plurality of memory circuits, a file size, and the stream number. 
     
     
         6 . The computing system of  claim 5 , wherein each DMA register maintains the plurality of designations until another DMA register message changing the plurality of designations is received. 
     
     
         7 . The computing system of  claim 1 , wherein each configurable logic circuit of the plurality of configurable logic circuits is further configured to include a designation of a second memory address and a tie stream number in one or more data transfer headers. 
     
     
         8 . The computing system of  claim 7 , wherein in response to receiving a data transfer including the designation of the second memory address and the tie stream number, each configurable logic circuit of the plurality of configurable logic circuits is further configured to forward the data transferred and the tie stream number to the second memory address. 
     
     
         9 . The computing system of  claim 1 , further comprising:
 a plurality of data communication lines coupling the plurality of configurable logic circuits in series, and wherein each configurable logic circuit of the plurality of configurable logic circuits is further configured to perform one or more data transfers through the plurality of data communication lines.   
     
     
         10 . A method of data transfer in a system, the system comprising a PCIe communication network, a plurality of memory circuits, and a plurality of configurable logic circuits, with each configurable logic circuit of the plurality of configurable logic circuits coupled to the PCIe communication network and to at least one memory circuit of the plurality of memory circuits, the method comprising:
 configuring each configurable logic circuit of the plurality of configurable logic circuits to generate a plurality of data transfers to any other configurable logic circuit of the plurality of configurable logic circuits; and   configuring each configurable logic circuit of the plurality of configurable logic circuits to generate a data packet, and for each data transfer of the plurality of data transfers, the data packet comprising a data transfer header having a plurality of designations comprising a first memory address of the plurality of memory circuits and a stream number of a plurality of stream numbers.   
     
     
         11 . The method of  claim 10 , wherein the system further comprises one or more processor circuits, the method further comprising:
 using the one or more processor circuits, transmitting a plurality of DMA register messages to one or more configurable logic circuits of the plurality of configurable logic circuits, each DMA register message having a plurality of designations comprising a selected memory address of the plurality of memory circuits, a selected file size, and a selected stream number of the plurality of stream numbers.   
     
     
         12 . The method of  claim 11 , further comprising:
 maintaining the plurality of designations in each DMA register until another DMA register message changing the one or more designations of the plurality of designations is received by the one or more configurable logic circuits of the plurality of configurable logic circuits.   
     
     
         13 . The method of  claim 10 , further comprising:
 configuring each configurable logic circuit of the plurality of configurable logic circuits to include a file size designation in each data transfer header.   
     
     
         14 . The method of  claim 10 , further comprising:
 configuring each configurable logic circuit of the plurality of configurable logic circuits to include a designation of a second memory address and a tie stream number in one or more data transfer headers.   
     
     
         15 . The method of  claim 14 , further comprising:
 configuring each configurable logic circuit of the plurality of configurable logic circuits to, in response to receiving a data transfer including the designation of the second memory address and the tie stream number, forward the data transferred and the tie stream number to the second memory address.   
     
     
         16 . The method of  claim 10 , wherein at least some data transfers of the plurality of data transfers occur in parallel and directly between or among the plurality of configurable logic circuits. 
     
     
         17 . A system comprising:
 a PCIe communication network comprising a PCIe switch and a plurality of PCIe communication lines;   a plurality of memory circuits;   a plurality of configurable logic circuits, each configurable logic circuit of the plurality of configurable logic circuits coupled to the PCIe communication network and to at least one memory circuit of the plurality of memory circuits, each configurable logic circuit of the plurality of configurable logic circuits configured to generate a plurality of data transfers to and from any other configurable logic circuit of the plurality of configurable logic circuits, each configurable logic circuit of the plurality of configurable logic circuits further configured to generate a data packet for each data transfer of the plurality of data transfers, the data packet comprising a data transfer header having a plurality of designations comprising a first memory address and a stream number; and   one or more processor circuits coupled to the PCIe communication network, wherein prior to commencement of a computing application to be performed by one or more configurable logic circuits of the plurality of configurable logic circuits, the one or more processor circuits are adapted to transmit a plurality of DMA register messages to the one or more configurable logic circuits of the plurality of configurable logic circuits, each DMA register message having a plurality of designations comprising a selected memory address of the plurality of memory circuits, a selected file size, and a selected stream number.   
     
     
         18 . The system of  claim 17 , wherein each data transfer header further comprises a file size designation, and wherein each DMA register maintains the plurality of designations until another DMA register message changing one or more designations of the plurality of designations is received. 
     
     
         19 . The system of  claim 17 , wherein configurable logic circuit of the plurality of configurable logic circuits is further configured to include a designation of a second memory address and a tie stream number in one or more data transfer headers. 
     
     
         20 . The system of  claim 19 , wherein in response to receiving a data transfer including the designation of the second memory address and the tie stream number, each configurable logic circuit of the plurality of configurable logic circuits is further configured to forward the data transferred and the tie stream number to the second memory address.