Apparatus and method for generating performance monitoring metrics

Abstract

An apparatus and method are described for generating performance metrics of a processor. For example, one embodiment of a processor comprises: one or more simultaneous multithreading cores to simultaneously execute multiple instruction threads; a plurality of performance monitor counters, each to maintain a count of events occurring as a result of the execution of the multiple instruction threads; and a performance monitor unit to generate a plurality of performance metric values using the event counts stored in the performance monitor counters and in response to receipt of a request from software for the performance metric values.

1 .- 27 . (canceled) 
     
     
         28 . A processor comprising:
 a plurality of performance monitor counters, each performance monitor counter to count events during processing of multiple instruction threads; and   one or more performance metric registers to store at least two different types of performance metric values generated based on counts of events stored in two or more performance monitor counters, the at least two different types of performance metric values including at least one of a number of successfully delivered micro-operations (uops) which eventually retire, a number of uops that never architecturally retire and/or slots wasted due to recovery from clears, a frequency with which a front end of the processor's pipeline delivers less than a maximum number of supported uops per cycle while a backend of the processor is ready to accept uops, and a frequency with which no uops were delivered for issuance due to a lack of back end processor resources.   
     
     
         29 . The processor as in  claim 28 , wherein a first set of bits in the performance metric register is to encode a first performance metric value of a first type and a second set of bits in the performance metric register is to encode a second performance metric value of a second type. 
     
     
         30 . The processor as in  claim 28 , wherein the performance monitor counters include fixed function performance monitor counters and/or programmable performance monitor counters. 
     
     
         31 . The processor as in  claim 30 , wherein the fixed function performance monitor counters include a first counter to count processor cycles and a second counter to count a number of instructions or micro-operations which have retired. 
     
     
         32 . The processor as in  claim 28 , further comprising a performance monitor circuit to dynamically generate the plurality of performance metric values in accordance with a corresponding plurality of performance metric definitions, the performance metric definitions constructed to be independent of any specific processor microarchitecture. 
     
     
         33 . The processor as in  claim 28 , further comprising a plurality of simultaneous multithreading cores, each multithreading core including at least one performance monitor circuit. 
     
     
         34 . The processor as in  claim 33 , wherein the simultaneous multithreading cores comprise hyperthreading cores.