Bit string operations using a computing tile

Abstract

Systems, apparatuses, and methods related to bit string operations using a computing tile are described. An example apparatus includes a plurality of computing devices (or “tiles”) coupled to a controller (e.g., and “orchestration controller”) and an interface. The controller can include circuitry to request data comprising a bit string having a first format that supports arithmetic operations to a first level of precision from a memory device (e.g., a memory array) coupled to the apparatus and cause the processing unit of at least one computing device of the plurality of computing devices to perform an operation in which the bit string is converted to a second format that supports arithmetic operations to a second level of precision that is different from the first level of precision.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a controller comprising a plurality of computing devices resident thereon, wherein each of the plurality of computing devices comprises a processing unit and a memory array configured as a cache for the processing unit; and   circuitry resident on the controller and coupled to the plurality of computing devices, wherein the circuitry is to:
 write data comprising a bit string having a first format that supports arithmetic operations to a first level of precision from a memory device couplable to the controller to a first memory array associated with a first computing device among the plurality of computing devices; 
 determine that an operation in which the bit string is converted to a second format that supports arithmetic operations to a second level of precision is to be performed using the second computing device; 
 write, in response to the determination, the bit string from the first memory array associated with the first computing device to a first memory array associated with the second computing device; and 
 cause a processing unit of the second computing device to perform the operation in which the bit string is converted to the second format. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the processing unit of at least one computing device among the plurality of computing devices is configured to perform an arithmetic operation or a logical operation, or both, using the bit string having the second format. 
     
     
         3 . The apparatus of  claim 1 , wherein at least one of the first format or the second format comprises a floating-point format and the other of the first format and the second format comprises a universal number format. 
     
     
         4 . The apparatus of  claim 1 , wherein at least one of the first format or the second format comprises an IEEE 754 format and the other of the first format and the second format comprises a Type III universal number format or a posit format. 
     
     
         5 . The apparatus of  claim 1 , further comprising a media controller coupled to the plurality of computing devices and comprising circuitry to perform read operations associated with the memory device, copy operations associated with the memory device, or error correction operations associated with the memory device, or any combination thereof. 
     
     
         6 . The apparatus of  claim 1 , wherein the circuitry is to cause the processing device of at least one computing device of the plurality of computing devices to perform an operation using the data in which at least some of the data is ordered, reordered, removed, or discarded, or any combination thereof. 
     
     
         7 . The apparatus of  claim 1 , wherein the processing unit of at least one computing device among the plurality of computing devices is a reduced instruction set computing device. 
     
     
         8 . A system, comprising:
 a memory device;   a storage controller resident on the memory device; and   a plurality of computing devices resident on the storage controller, wherein:
 the computing devices each comprise a respective memory resource and a respective processing unit, and 
 the computing devices are to:
 receive respective streams of data comprising one or more bit strings; and 
 perform operations using the one or more bit strings to convert the one or more bit strings form a first format that supports arithmetic operations to a first level of precision to a second format that supports arithmetic operations to a second level of precision. 
 
   
     
     
         9 . The system of  claim 8 , further comprising a communication subsystem coupled to the plurality of computing devices, wherein the communication subsystem is to provide communications pathways to allow at least one computing device to access an address space associated with a different computing device. 
     
     
         10 . The system of  claim 8 , further comprising circuitry coupled to the computing devices, wherein the circuitry is to allocate particular computing devices among the plurality of computing devices to perform the operations using the one or more bit strings. 
     
     
         11 . The system of  claim 8 , wherein at least one of the computing devices is to initiate the operations using the one or more bit strings in response to receipt of an initiation command, and wherein the computing devices are to receive the respective streams of data and perform the operations using the one or more bit strings in the absence of a command subsequent to the initiation command. 
     
     
         12 . The system of  claim 8 , wherein at least one of the computing devices is to perform an arithmetic operation or a logical operation, or both, using one or more bit strings having the second format. 
     
     
         13 . The system of  claim 8 , wherein the computing devices further comprise respective direct media access (DMA) buffering components to:
 buffer subsequent bit strings received as part of the respective streams of data while the operations are performed on preceding bit strings; and   cause the subsequent bit strings to be transferred to the respective memory resources in response to completion of the operations on the preceding bit strings.   
     
     
         14 . A method, comprising:
 writing, by circuitry coupled to a plurality of computing devices resident on a storage controller, data comprising a bit string having a first format that supports arithmetic operations to a first level of precision from a memory device couplable to the controller to a memory array associated with a first computing device among the plurality of computing devices;   determining that an operation in which the bit string is converted to a second format that supports arithmetic operations to a second level of precision is to be performed using a second computing device among the plurality of computing devices;   writing, in response to the determination, the bit string from the memory array associated with the first computing device to a memory array associated with the second computing device; and   performing, by a processing unit of the second computing device, the operation in which the bit string is converted to the second format.   
     
     
         15 . The method of  claim 14 , further comprising performing, using the processing unit of at least one of the first computing device or the second computing device, an arithmetic operation or a logical operation, or both, using the bit string having the second format. 
     
     
         16 . The method of  claim 14 , further comprising:
 determining that at least one sub-operation is to be performed as part of the arithmetic operation, the logical operation, or both;   sending a command to a computing device different than the first computing device or the second computing device to cause performance of the sub-operation; and   performing, using the computing device that is different than the first computing device or the second computing device, the sub-operation as part of performance of the arithmetic operation, the logical operation, or both.   
     
     
         17 . The method of  claim 14 , wherein at least one of the first format or the second format comprises a floating-point format and the other of the first format and the second format comprises a universal number format. 
     
     
         18 . The method of  claim 14 , wherein at least one of the first format or the second format comprises an IEEE 754 format and the other of the first format and the second format comprises a Type III universal number format or a posit format. 
     
     
         19 . The method of  claim 14 , further comprising performing, using the processing unit of at least one of the first computing device or the second computing device, an operation in which at least some of the data is ordered, reordered, removed, or discarded, or any combination thereof. 
     
     
         20 . The method of  claim 14 , wherein the processing unit of at least one computing device among the plurality of computing devices is configured with a reduced instruction set architecture.