On-chip reference current generating circuit

Abstract

Embodiment provides an on-chip reference current generating circuit for supplying at least one reference current to at least one load. The on-chip reference current generating circuit includes a transistor, an operational amplifier unit, a first pull-down resistor unit, and a current mirror unit. A reference voltage is inputted to a positive input terminal of the operational amplifier unit, a negative input terminal of the operational amplifier unit is coupled to a source of the transistor, and an output terminal of the operational amplifier unit is coupled to a gate of the transistor. As a resistor unit calibrated by a ZQ calibration circuit, the first pull-down resistor unit is coupled between the source of the transistor and a ground. The current mirror unit is coupled between a drain of the transistor and a power supply voltage and is configured to output a generated current to the load for use.

What is claimed is: 
     
         1 . An on-chip reference current generating circuit for supplying at least one reference current to at least one load, the on-chip reference current generating circuit comprising:
 a transistor;   an operational amplifier unit, a reference voltage being inputted to a positive input terminal of the operational amplifier unit, a negative input terminal of the operational amplifier unit being coupled to a source of the transistor, and an output terminal of the operational amplifier unit being coupled to a gate of the transistor;   a first pull-down resistor unit coupled between the source of the transistor and a ground, the first pull-down resistor unit being a resistor unit calibrated by a ZQ calibration circuit; and   a current mirror unit coupled between a drain of the transistor and a power supply voltage, wherein the current mirror unit is configured to output a generated current to the load for use.   
     
     
         2 . The on-chip reference current generating circuit according to  claim 1 , wherein the ZQ calibration circuit has a second pull-down resistor unit and a second pull-down calibration code configured for calibrating the second pull-down resistor unit, wherein
 the first pull-down resistor unit is configured to duplicate the second pull-down resistor unit, and use the second pull-down calibration code as a first pull-down calibration code of the first pull-down resistor unit.   
     
     
         3 . The on-chip reference current generating circuit according to  claim 2 , wherein the first pull-down resistor unit is arranged adjacent to the second pull-down resistor unit. 
     
     
         4 . The on-chip reference current generating circuit according to  claim 1 , wherein the reference voltage is less than 2(V GS −V TH ). 
     
     
         5 . The on-chip reference current generating circuit according to  claim 4 , wherein the reference voltage is 1/100˜ 1/10 of 2(V GS −V TH ). 
     
     
         6 . The on-chip reference current generating circuit according to  claim 1 , further comprising a shunt resistor unit connected in parallel with the first pull-down resistor unit, wherein the shunt resistor unit is enabled before the first pull-down resistor unit is calibrated by the ZQ calibration circuit, and the shunt resistor unit is disabled after the first pull-down resistor unit is calibrated by the ZQ calibration circuit. 
     
     
         7 . The on-chip reference current generating circuit according to  claim 6 , wherein the shunt resistor unit comprises at least one transistor. 
     
     
         8 . The on-chip reference current generating circuit according to  claim 7 , wherein the source of the at least one transistor in the shunt resistor unit is grounded. 
     
     
         9 . The on-chip reference current generating circuit according to  claim 1 , wherein the first pull-down resistor unit comprises a plurality of transistors coupled in parallel. 
     
     
         10 . The on-chip reference current generating circuit according to  claim 1 , further comprising a bandgap voltage generator, wherein the bandgap voltage generator is coupled to the positive input terminal of the operational amplifier unit and is configured to generate the reference voltage. 
     
     
         11 . The on-chip reference current generating circuit according to  claim 1 , wherein the transistor is an N-type transistor. 
     
     
         12 . A chip, comprising an on-chip reference current generating circuit for supplying at least one reference current to at least one load, wherein the on-chip reference current generating circuit comprises:
 a transistor;   an operational amplifier unit, a reference voltage being inputted to a positive input terminal of the operational amplifier unit, a negative input terminal of the operational amplifier unit being coupled to a source of the transistor, and an output terminal of the operational amplifier unit being coupled to a gate of the transistor;   a first pull-down resistor unit coupled between the source of the transistor and a ground, the first pull-down resistor unit being a resistor unit calibrated by a ZQ calibration circuit; and   a current mirror unit coupled between a drain of the transistor and a power supply voltage, wherein the current mirror unit is configured to output a generated current to the load for use.   
     
     
         13 . The chip according to  claim 12 , wherein the ZQ calibration circuit has a second pull-down resistor unit and a second pull-down calibration code configured for calibrating the second pull-down resistor unit, wherein
 the first pull-down resistor unit is configured to duplicate the second pull-down resistor unit, and use the second pull-down calibration code as a first pull-down calibration code of the first pull-down resistor unit.   
     
     
         14 . The chip according to  claim 13 , wherein the first pull-down resistor unit is arranged adjacent to the second pull-down resistor unit. 
     
     
         15 . The chip according to  claim 12 , wherein the reference voltage is less than 2(V GS −V TH ). 
     
     
         16 . The chip according to  claim 12 , wherein the on-chip reference current generating circuit further comprises a shunt resistor unit connected in parallel with the first pull-down resistor unit, wherein the shunt resistor unit is enabled before the first pull-down resistor unit is calibrated by the ZQ calibration circuit, and the shunt resistor unit is disabled after the first pull-down resistor unit is calibrated by the ZQ calibration circuit. 
     
     
         17 . The chip according to  claim 16 , wherein the shunt resistor unit comprises at least one transistor. 
     
     
         18 . The chip according to  claim 17 , wherein the source of the at least one transistor in the shunt resistor unit is grounded. 
     
     
         19 . The chip according to  claim 12 , wherein the first pull-down resistor unit comprises a plurality of transistors coupled in parallel. 
     
     
         20 . The chip according to  claim 12 , wherein the on-chip reference current generating circuit further comprises a bandgap voltage generator, wherein the bandgap voltage generator is coupled to the positive input terminal of the operational amplifier unit and is configured to generate the reference voltage.