Method for embedding silicon die into a stacked package

Abstract

Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment, the configuration includes a substrate with a recess, a first die carried by the substrate wherein the die substantially covers the recess, and a logic component carried by the die in a location exposed by the recess. The logic component can be substantially coplanar with the substrate. The die is electrically connected to a terminal on a one side of the substrate, and the logic component is electrically connected to a terminal on an opposite side of the substrate.

I/We claim: 
     
         1 . A semiconductor device package, comprising:
 an interposer substrate with an opening extending through the interposer substrate from a first outer surface to a second outer surface;   a first semiconductor die attached to the first outer surface of the interposer substrate over the opening;   a second semiconductor die attached to the first semiconductor die and disposed at least partially within the opening; and   wire bonds electrically connecting the second semiconductor die to bond pads on the second outer surface of the interposer substrate.   
     
     
         2 . The semiconductor device package of  claim 1  further comprising a third semiconductor die attached to the first semiconductor die opposite the first outer surface. 
     
     
         3 . The semiconductor device package of  claim 2 , wherein the third semiconductor die is electrically coupled to the second semiconductor die by one or more interconnects. 
     
     
         4 . The semiconductor device package of  claim 3 , wherein the one or more interconnects comprise wirebonds and/or through-silicon vias. 
     
     
         5 . The semiconductor device package of  claim 2  wherein the third semiconductor die is separated from the semiconductor die by a spacer. 
     
     
         6 . The semiconductor device package of  claim 1 , wherein the first semiconductor die completely overlaps the opening. 
     
     
         7 . The semiconductor device package of  claim 1 , wherein the opening is centrally located on the interposer substrate. 
     
     
         8 . The semiconductor device package of  claim 1 , wherein the first semiconductor die comprises a NAND memory die and wherein the second semiconductor die comprises a controller. 
     
     
         9 . The semiconductor device package of  claim 1 , wherein the second semiconductor die has a third outer surface opposite the first semiconductor die and wherein the third outer surface is flush with the second outer surface. 
     
     
         10 . The semiconductor device package of  claim 1 , wherein a portion of the second semiconductor die projects outside of the opening and beyond the interposer substrate. 
     
     
         11 . The semiconductor device package of  claim 1 , wherein the opening has a first planform area and wherein the second semiconductor die has a second planform area substantially the same as the first planform area. 
     
     
         12 . A semiconductor device package, comprising:
 an interposer substrate with an opening extending through the interposer substrate from a first outer surface to a second outer surface;   a stack of memory dies attached to the first outer surface of the interposer substrate over the opening;   a controller die attached to the stack of memory dies and disposed at least partially within the opening; and   wire bonds electrically connecting the controller die to bond pads on the second outer surface of the interposer substrate.   
     
     
         13 . The semiconductor device package of  claim 12 , wherein the stack of memory die are electrically coupled to one another and to the interposer substrate by one or more interconnects. 
     
     
         14 . The semiconductor device package of  claim 13 , wherein the one or more interconnects comprise wire bonds or through-silicon vias (TSVs). 
     
     
         15 . The semiconductor device package of  claim 12 , wherein the opening has a first planform area and wherein the controller die has a second planform area substantially the same as the first planform area. 
     
     
         16 . The semiconductor device package of  claim 12 , wherein the stack of memory dies completely overlaps the opening. 
     
     
         17 . The semiconductor device package of  claim 12 , wherein the opening is centrally located on the interposer substrate. 
     
     
         18 . The semiconductor device package of  claim 12 , wherein the controller die has a third outer surface opposite the stack of memory dies and wherein the third outer surface is flush with the second outer surface. 
     
     
         19 . The semiconductor device package of  claim 12 , wherein a portion of the controller die projects outside of the opening and beyond the interposer substrate. 
     
     
         20 . A semiconductor device package, comprising:
 an interposer substrate with an opening extending through the interposer substrate from a first outer surface to a second outer surface;   a stack of memory dies disposed over the opening and having a lower surface attached to the first outer surface of the interposer substrate along a periphery of the opening;   a controller die attached to the lower surface of the stack of memory dies and disposed at least partially within the opening; and   wire bonds electrically connecting the controller die to bond pads on the second outer surface of the interposer substrate.