High Speed, Parallel Configuration of Multiple Field Programmable Gate Arrays

Abstract

Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration.

It is claimed: 
     
         1 . A method of configuring a computing system having a first configuration bit image for a first application stored in a memory circuit, the method comprising:
 configuring a first configurable logic circuit with a communication functionality, the communication functionality provided in a second configuration bit image stored in a nonvolatile memory;   using a processor circuit, transmitting a first message to the first configurable logic circuit, the first message comprising a first memory address of the first configuration bit image in the memory circuit;   using a DMA engine of the first configurable logic circuit, accessing the memory circuit and obtaining the first configuration bit image;   using the first configuration bit image, the first configurable logic circuit self-configuring for the first application; and   using the first field programmable gate array, transmitting the first configuration bit image to at least one second field programmable gate array of the plurality of field programmable gate arrays.   
     
     
         2 . The method of  claim 1 , further comprising:
 using the first configurable logic circuit, transmitting the first configuration bit image to a second configurable logic circuit.   
     
     
         3 . The method of  claim 2 , further comprising:
 using the first configuration bit image transmitted from the first configurable logic circuit, configuring the second configurable logic circuit.   
     
     
         4 . The method of  claim 1 , wherein the first configuration bit image is transmitted to the second configurable logic circuit through one or more JTAG communication lines. 
     
     
         5 . The method of  claim 1 , wherein the communication functionality is PCIe. 
     
     
         6 . The method of  claim 1 , wherein the message further comprises a file size of the first configuration bit image. 
     
     
         7 . The method of  claim 1 , further comprising:
 configuring the DMA engine in the first configurable logic circuit, the DMA engine functionality provided in a third configuration bit image stored in the nonvolatile memory.   
     
     
         8 . The method of  claim 1 , wherein the first message is transmitted to the first configurable logic circuit through a plurality of PCIe communication lines. 
     
     
         9 . The method of  claim 1 , further comprising:
 using the processor circuit, transmitting a second message to the first configurable logic circuit, the second message comprising a second memory address in the memory circuit of a third configuration bit image for a second application;   using the DMA engine of the first configurable logic circuit, accessing the memory circuit and obtaining the third configuration bit image; and   using the third configuration bit image, the first configurable logic circuit self-reconfiguring for the second application.   
     
     
         10 . A computing system comprising:
 a memory circuit storing a first configuration bit image for a first application;   a processor circuit adapted to transmit a first message comprising a first memory address of the first configuration bit image in the memory circuit;   one or more nonvolatile memories, each nonvolatile memory storing a second configuration bit image for a communication functionality; and   a first configurable logic circuit coupled to the processor circuit and coupled to a nonvolatile memory of the one or more nonvolatile memories, the first configurable logic circuit configured for the communication functionality using the second configuration bit image, the first configurable logic circuit having a DMA engine and, in response to the first message, configured to use the DMA engine to access the memory circuit, obtain the first configuration bit image, and to self-configure for the first application using the first configuration bit image.   
     
     
         11 . The computing system of  claim 10 , further comprising:
 at least one second configurable logic circuit coupled to the first configurable logic circuit, the first configurable logic circuit configured to transmit the first configuration bit image to the at least one second configurable logic circuit.   
     
     
         12 . The computing system of  claim 11 , wherein the at least one second configurable logic circuit is configured for the first application using the first configuration bit image. 
     
     
         13 . The computing system of  claim 11 , further comprising:
 one or more JTAG communication lines coupling the first configurable logic circuit to the at least one second configurable logic circuit for transmission of the first configuration bit image.   
     
     
         14 . The computing system of  claim 10 , further comprising:
 a PCIe switch; and   a plurality of PCIe communication lines coupling the first field configurable logic circuit through the PCIe switch to the processor circuit.   
     
     
         15 . The computing system of  claim 14 , wherein the communication functionality is PCIe. 
     
     
         16 . The computing system of  claim 14 , wherein the first message is transmitted to the first configurable logic circuit through the plurality of PCIe communication lines. 
     
     
         17 . The computing system of  claim 10 , wherein the first message further comprises a file size of the first configuration bit image. 
     
     
         18 . The computing system of  claim 10 , wherein the first configurable logic circuit is configured for the DMA engine functionality using a third configuration bit image stored in the nonvolatile memory. 
     
     
         19 . The computing system of  claim 10 , wherein in response to a second message transmitted from the processor circuit, the second message comprising a second memory address in the memory circuit for a third configuration bit image for a second application, the first configurable logic circuit is configured to access the memory circuit, obtain the third configuration bit image, and to reconfigure for the second application using the third configuration bit image. 
     
     
         20 . A configurable computing system comprising:
 a memory circuit storing a first configuration bit image for an application;   one or more nonvolatile memories, each nonvolatile memory storing a second configuration bit image for a communication functionality;   a first configurable logic circuit coupled to a nonvolatile memory of the one or more nonvolatile memories, the first configurable logic circuit configured for the communication functionality using the second configuration bit image, the first configurable logic circuit having a DMA engine and, in response to a message comprising a memory address of the first configuration bit image in the memory circuit, the first configurable logic circuit is configured to use the DMA engine to access the memory circuit, obtain the first configuration bit image, and self-configure for the application using the first configuration bit image; the first configurable logic circuit further configured to transmit the first configuration bit image over one or more communication lines; and   at least one second configurable logic circuit coupled to the one or more communication lines, the at least one second configurable logic circuit configured for the application using the first configuration bit image transmitted over the one or more communication lines.