System and method for mixed tile-aware and tile-unaware traffic through a tile-based address aperture

Abstract

In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

1 - 15 . (canceled) 
     
     
         16 . A method for intelligent tile-based memory bandwidth management in a portable computing device (“PCD”), the method comprising:
 a tile-aware processing component detecting a data access request from a tile-unaware processing component directed to an address aperture in communication with a memory component having a tile-based address structure, wherein the data access request is associated with a linear aperture address; and 
 in response to detecting the data access request, the tile-aware processing component generating a plurality of linear aperture addresses representing a plurality of tile-based addresses in an alias address region of the memory component, wherein the plurality of linear aperture addresses collectively correspond to an entire tile. 
 
     
     
         17 . The method of  claim 16 , wherein the data access request comprises a data read request for data stored in the memory component, and the method further comprises:
 providing the plurality of linear aperture addresses to the address aperture;   receiving the entire tile from the address aperture in response to the plurality of linear aperture addresses; and   storing the entire tile in a cache memory associated with the tile-unaware processing component.   
     
     
         18 . The method of  claim 17 , further comprising, before detecting the data access request, the tile-unaware processing component providing tile information to the tile-aware processing component, the tile information defining an array of tiles within an image comprising an array of linear aperture addresses. 
     
     
         19 . The method of  claim 16 , wherein the data access request comprises a data write request, and the method further comprises:
 determining whether the data write request has been serviced by the address aperture;   in response to determining that the data write request has been serviced by the address aperture, determining whether a cache memory associated with the tile-unaware processing component contains valid data in all locations corresponding to the plurality of linear aperture addresses; and   in response to determining that the cache memory contains valid data in all locations corresponding to the plurality of linear aperture addresses, evicting data from a plurality of locations in the cache memory corresponding to the plurality of linear aperture addresses.   
     
     
         20 . The method of  claim 19 , further comprising, before detecting the data access request, the tile-unaware processing component providing tile information to the tile-aware processing component, the tile information defining an array of tiles within an image comprising an array of linear aperture addresses. 
     
     
         21 . The method of  claim 16 , wherein the data access request comprises a bit block transfer request identifying one or more data blocks, the method further comprising:
 determining one or more tiles corresponding to one or more data blocks identified in the bit block transfer request;   providing the plurality of linear aperture addresses to the address aperture;   receiving the entire tile from the address aperture in response to the plurality of linear aperture addresses;   storing the entire tile in a non-tile-based memory region; and   for each of zero or more further tiles of the one or more tiles, repeating the generating, providing, receiving, and storing steps.   
     
     
         22 . The method of  claim 21 , wherein the non-tile-based memory region is a cache memory associated with the tile-unaware processing component. 
     
     
         23 . A system for intelligent tile-based memory bandwidth management in a portable computing device (“PCD”), the system comprising:
 a tile-unaware processing component configured to provide a data access request directed to an address aperture in communication with a memory component having a tile-based address structure, wherein the data access request is associated with a linear aperture address; and 
 a tile-aware processing component associated with the tile-unaware processing component and configured to detect the data access request and, in response to detecting the data access request, generate a plurality of linear aperture addresses representing a plurality of tile-based addresses in an alias address region of the memory component, wherein the plurality of linear aperture addresses collectively correspond to an entire tile. 
 
     
     
         24 . The system of  claim 23 , wherein the data access request comprises a data read request for data stored in the memory component, and the tile-aware processing component is further configured to:
 provide the plurality of linear aperture addresses to the address aperture;   receive the entire tile from the address aperture in response to the plurality of linear aperture addresses; and   store the entire tile in a cache memory associated with the tile-unaware processing component.   
     
     
         25 . The system of  claim 24 , wherein the tile-unaware processing component is further configured, before detecting the data access request, to provide tile information to the tile-aware processing component, the tile information defining an array of tiles within an image comprising an array of linear aperture addresses. 
     
     
         26 . The system of  claim 23 , wherein the data access request comprises a data write request, and the tile-aware processing component is further configured to:
 determine whether the data write request has been serviced by the address aperture;   in response to determining that the data write request has been serviced by the address aperture, determine whether a cache memory associated with the tile-unaware processing component contains valid data in all locations corresponding to the plurality of linear aperture addresses; and   in response to determining that the cache memory contains valid data in all locations corresponding to the plurality of linear aperture addresses, evict data from a plurality of locations in the cache memory corresponding to the plurality of linear aperture addresses.   
     
     
         27 . The system of  claim 26 , wherein the tile-aware processing component is further configured, before detecting the data access request, to provide tile information to the tile-aware processing component, the tile information defining an array of tiles within an image comprising an array of linear aperture addresses. 
     
     
         28 . The system of  claim 23 , wherein the data access request comprises a bit block transfer request identifying one or more data blocks, and the tile-aware processing component is further configured to:
 determine one or more tiles corresponding to one or more data blocks identified in the bit block transfer request;   provide the plurality of linear aperture addresses to address aperture;   receiving the entire tile from the address aperture in response to the plurality of linear aperture addresses;   store the entire tile in a non-tile-based memory region; and   for each of zero or more further tiles of the one or more tiles, repeat the generating, providing, receiving, and storing steps.   
     
     
         29 . The system of  claim 28 , wherein the non-tile-based memory region is a cache memory associated with the tile-unaware processing component. 
     
     
         30 . The system of  claim 23 , wherein the PCD is a wireless telephone.