Power-on reset circuit

Abstract

An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.

What is claimed is: 
     
         1 . An integrated circuit (IC), comprising:
 a power-on reset (POR) circuit coupled to a supply voltage terminal and having first and second control outputs, the POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage terminal exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage; and   a digital logic circuit having a first control input coupled to the first control output of the POR circuit and having a second control input coupled to the second control output of the POR circuit, the digital logic circuit is configured to initiate a first transaction responsive to assertion of the first control signal and to initiate a second transaction responsive to assertion of the second control signal.   
     
     
         2 . The IC of  claim 1 , wherein the second threshold voltage is greater than the first threshold voltage. 
     
     
         3 . The IC of  claim 2 , wherein the POR circuit includes first and second comparators, the first comparator having an output to produce the first control signal and the second comparator having an output to produce the second control signal. 
     
     
         4 . The IC of  claim 2 , wherein the POR circuit includes:
 a voltage divider coupled to the supply voltage terminal and a common terminal and having a first voltage divider terminal and a second voltage divider terminal;   a first comparator coupled to the first voltage divider terminal, the first comparator having a comparator output to produce the first control signal; and   a second comparator coupled to the second voltage divider terminal, the second comparator having a comparator output to produce the second control signal.   
     
     
         5 . The IC of  claim 4 , further including a reference voltage generator coupled to the first and second comparators. 
     
     
         6 . The IC of  claim 5 , wherein
 the first comparator has a noninverting input and an inverting input, the first voltage divider terminal is coupled to the noninverting input of the first comparator, and the reference voltage generator is coupled to the inverting input of the first comparator; and   the second comparator has a noninverting input and an inverting input, the second voltage divider terminal is coupled to the noninverting input of the second comparator, and the reference voltage generator is coupled to the inverting input of the second comparator.   
     
     
         7 . The IC of  claim 4 , wherein the voltage divider includes first, second, and third resistors coupled in series between the supply voltage terminal and the common terminal, the first voltage divider terminal is between the first and second resistors, and the second voltage divider terminal is between the second and third resistors. 
     
     
         8 . The IC of  claim 1 , wherein the digital logic circuit is configured to avoid initiating a subsequent transaction responsive to a subsequent assertion of the second control signal following a power-on event. 
     
     
         9 . A circuit, comprising:
 a voltage divider coupled between a supply voltage terminal and a common terminal and having a first voltage divider terminal and a second voltage divider terminal;   a reference voltage generator;   a first comparator coupled to the first voltage divider terminal and to the reference voltage generator, the first comparator having a comparator output to produce a first control signal; and   a second comparator coupled to the second voltage divider terminal and to the reference voltage generator, the second comparator having a comparator output to produce a second control signal.   
     
     
         10 . The circuit of  claim 9 , wherein the voltage divider includes first, second, and third resistors coupled in series between the supply voltage terminal and the common terminal, the first voltage divider terminal is between the first and second resistors, and the second voltage divider terminal is between the second and third resistors. 
     
     
         11 . The circuit of  claim 9 , wherein:
 the first comparator has a noninverting input and an inverting input, the first voltage divider terminal is coupled to the noninverting input of the first comparator, and the reference voltage generator is coupled to the inverting input of the first comparator; and   the second comparator has a noninverting input and an inverting input, the second voltage divider terminal is coupled to the noninverting input of the second comparator, and the reference voltage generator is coupled to the inverting input of the second comparator.   
     
     
         12 . The circuit of  claim 9 , further including a digital logic circuit having a first control input and a second control input, the first control input is coupled to the comparator output of the first comparator and the second control input is coupled to the comparator output of the second comparator.