US2021193049A1PendingUtilityA1

Electronic Display with In-Pixel Compensation and Oxide Drive Transistors

Assignee: APPLE INCPriority: Dec 23, 2019Filed: Oct 20, 2020Published: Jun 24, 2021
Est. expiryDec 23, 2039(~13.4 yrs left)· nominal 20-yr term from priority
H10D 86/471H10D 86/481H10D 86/60H10D 86/423G09G 2320/0247G09G 2320/0238G09G 2320/0209G09G 2310/0256G09G 2300/0842G09G 2300/0819G09G 2300/0465G09G 2300/0417G09G 3/3233G09G 3/2092G09G 2300/0861G09G 3/3266G09G 3/3291H10K 59/1216H10K 59/1213H10K 59/126
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Claims

Abstract

A display pixel may include an organic light-emitting diode, one or more emission transistors, a drive transistor, a gate setting transistor, a data loading transistor, and an initialization transistor. The drive transistor may be implemented as a semiconducting-oxide transistor to mitigate threshold voltage hysteresis to improve first frame response at high refresh rates, to reduce undesired luminance jumps at low refresh rates, and to reduce image sticking. The gate setting transistor may also be implemented as a semiconducting-oxide transistor to reduce leakage at the gate terminal of the drive transistor. The initialization transistor may also be implemented as a semiconducting-oxide transistor so that it can be controlled using a shared emission signal to reduce routing complexity. The remaining transistors in the pixel may be implemented as p-type silicon transistors. Display pixels configured in this way can support in-pixel threshold voltage compensation and on-bias stress phase to further mitigate the hysteresis.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A display pixel, comprising:
 an organic light-emitting diode having an anode terminal and a cathode terminal;   a semiconducting-oxide drive transistor coupled in series with the organic light-emitting diode, wherein the semiconducting-oxide drive transistor has a gate terminal, a drain terminal, and a source terminal; and   a storage capacitor having a first terminal coupled to the gate terminal of the semiconducting-oxide drive transistor and a second terminal coupled to the anode terminal of the organic light-emitting diode.   
     
     
         2 . The display pixel of  claim 1 , further comprising:
 a semiconducting-oxide gate voltage setting transistor coupled across the drain terminal and the gate terminal of the semiconducting-oxide drive transistor.   
     
     
         3 . The display pixel of  claim 1 , further comprising:
 an initialization line on which an initialization voltage is provided; and   a semiconducting-oxide initialization transistor coupled between the initialization line and the anode terminal of the organic light-emitting diode.   
     
     
         4 . The display pixel of  claim 2 , further comprising:
 an initialization line on which an initialization voltage is provided; and   a semiconducting-oxide initialization transistor coupled between the initialization line and the anode terminal of the organic light-emitting diode.   
     
     
         5 . The display pixel of  claim 4 , further comprising:
 a p-type silicon emission transistor coupled in series between the semiconducting-oxide drive transistor and the anode terminal of the organic light-emitting diode.   
     
     
         6 . The display pixel of  claim 5 , wherein the p-type silicon emission transistor and the semiconducting-oxide initialization transistor are configured to receive an emission control signal generated by an emission control circuit. 
     
     
         7 . The display pixel of  claim 5 , further comprising:
 a positive power supply line; and   an additional p-type silicon emission transistor coupled in series between the positive power supply line and the semiconducting-oxide drive transistor.   
     
     
         8 . The display pixel of  claim 7 , further comprising:
 a data line; and   a p-type silicon data loading transistor coupled between the data line and the source terminal of the semiconducting-oxide drive transistor.   
     
     
         9 . The display pixel of  claim 8 , further comprising:
 a first scan line configured to provide a first scan signal to the semiconducting-oxide gate voltage setting transistor; and   a second scan line configured to provide a second scan signal to the p-type silicon data loading transistor.   
     
     
         10 . The display pixel of  claim 1 , wherein the storage capacitor is stacked above the semiconducting-oxide drive transistor to provide shielding for the semiconducting-oxide drive transistor. 
     
     
         11 . The display pixel of  claim 1 , wherein the semiconducting-oxide drive transistor comprises:
 active semiconducting-oxide material;   a top gate conductor formed above the active semiconducting-oxide material; and   a bottom gate conductor that is formed below the active semiconducting-oxide material and that is coupled to a selected one of the gate terminal or the source terminal of the semiconducting-oxide drive transistor.   
     
     
         12 . A display, comprising:
 a silicon transistor;   a semiconducting-oxide transistor formed above the silicon transistor; and   a storage capacitor stacked above the semiconducting-oxide transistor, wherein the storage capacitor is configured to reduce pixel crosstalk and to prevent hydrogen from penetrating into a channel of the semiconducting-oxide transistor by at least partially shielding the semiconducting-oxide transistor.   
     
     
         13 . The display of  claim 12 , wherein the storage capacitor has a first terminal directly connected to a gate terminal of the semiconducting-oxide transistor and a second terminal directly connected to a drain terminal of the silicon transistor. 
     
     
         14 . The display of  claim 12 , wherein the semiconducting-oxide transistor has a bottom gate conductor, wherein the silicon transistor has a top gate conductor, and wherein the bottom gate conductor of the semiconducting-oxide transistor and the top gate conductor of the silicon transistor are formed from the same conductive layer. 
     
     
         15 . The display of  claim 12 , wherein the semiconducting-oxide transistor comprises:
 a first gate conductor; and   a second gate conductor coupled to a selected one of a gate terminal or a source terminal of the semiconducting-oxide transistor.   
     
     
         16 . The display of  claim 12 , wherein the semiconducting-oxide transistor has a gate conductor configured as a bottom plate of the storage capacitor. 
     
     
         17 . The display of  claim 12 , wherein the storage capacitor has a top plate that covers the gate conductor of the semiconducting-oxide transistor, and wherein the top plate of the storage capacitor provides electrical shielding and optical shielding for the semiconducting-oxide transistor. 
     
     
         18 . A display comprising:
 a light-emitting diode having an anode terminal and a cathode terminal;   a first semiconducting-oxide transistor having semiconducting oxide material formed in a first layer and having a first gate conductor, wherein the first semiconducting-oxide transistor comprises a drive transistor coupled to the anode terminal of the light-emitting diode; and   a second semiconducting-oxide transistor having semiconducting material formed in a second layer different than the first layer and having a second gate conductor.   
     
     
         19 . The display of  claim 18 , wherein the first gate conductor and the second gate conductor are formed in the same gate layer. 
     
     
         20 . The display of  claim 18 , further comprising:
 a first gate metal formed below the semiconducting material of the first semiconducting-oxide transistor; and   a second gate metal formed below the semiconducting material of the second semiconducting-oxide transistor, wherein the first gate metal and the second gate metal are formed in the same gate metal layer.   
     
     
         21 . The display of  claim 18 , further comprising only one planarization layer formed between the anode terminal and the first gate conductor. 
     
     
         22 . The display of  claim 18 , wherein the first layer is above or below the second layer. 
     
     
         23 . The display of  claim 18 , further comprising:
 a storage capacitor having a first terminal formed in the same gate layer as the first gate conductor.   
     
     
         24 . The display of  claim 23 , wherein the storage capacitor has a second terminal formed in a metal layer above the first terminal.

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