Low-power flip flop circuit

Abstract

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

What is claimed is: 
     
         1 . A method to operate a flip-flop circuit, comprising:
 receiving a scan-in signal and a data signal;   selectively coupling either the scan-in signal or the data signal to coupled master and slave latches; and   based on a clock signal, selectively activating either the master latch or the slave latch so as to latch either the scan-in signal or the data signal as an output signal of the flip-flop circuit.   
     
     
         2 . The method of  claim 1 , wherein the master latch circuit comprises a pair of cross-coupled OR-AND-Inverter (OAI) logic gates, and the slave latch circuit comprises a pair of cross-coupled AND-OR-Inverter (AOI) logic gates, and wherein the master and slave latch circuits each comprises at most two transistors configured to receive the clock signal. 
     
     
         3 . The method of  claim 2 , wherein the at most two transistors of the first and second latch circuits, respectively, each receives the clock signal at a respective gate. 
     
     
         4 . The method of  claim 2 , further comprising:
 selecting either a data signal or a scan-in signal as the input signal in response to an enable signal.   
     
     
         5 . The method  claim 4 , further comprising:
 providing a logically inverted clock signal to the at most two transistors of the first latch circuit and the at most two transistors of the second latch circuit, respectively.   
     
     
         6 . The method of  claim 1 , wherein the at most two transistors of the first and second latch circuits, respectively, comprise a p-type metal-oxide-semiconductor transistor and an n-type metal-oxide-semiconductor transistor. 
     
     
         7 . The method of  claim 1 , further comprising:
 delaying the clock signal to the master latch circuit but not delaying the clock signal to the slave latch circuit.   
     
     
         8 . A method of operating a flip-flop circuit, comprising:
 in response to a clock signal, complementarily activating first and second latch circuits so as to latch a first input signal to an output signal via the first latch circuit, or latch a second input signal to the output signal via the second latch circuit; and   delaying the clock signal to the first latch circuit, but not delaying the clock signal to the second latch circuit.   
     
     
         9 . The method of  claim 8 , wherein the first and second latch circuits each comprises at most two transistors configured to receive the clock signal, wherein the first latch circuit includes a pair of cross-coupled OR-AND-Inverter (OAI) logic gates, and the second latch circuit includes a pair of cross-coupled AND-OR-Inverter (AOI) logic gates. 
     
     
         10 . The method of  claim 9 , wherein the at most two transistors of the first and second latch circuits, respectively, each receives the clock signal at a respective gate. 
     
     
         11 . The method of  claim 9 , wherein the at most two transistors of the first and second latch circuits, respectively, comprise a p-type metal-oxide-semiconductor transistor and an n-type metal-oxide-semiconductor transistor. 
     
     
         12 . The method of  claim 9 , wherein
 the first input signal comprises a scan-in signal; and   the second input signals comprises a data signal.   
     
     
         13 . The method of  claim 9 , further comprising:
 providing a logically inverted clock signal to the at most two transistors of the first latch circuit and the at most two transistors of the second latch circuit, respectively.   
     
     
         14 . A method of operating a flip-flop circuit, the method, comprising:
 receiving a clock signal by a first circuit;   receiving the clock signal by a second circuit coupled to the first circuit;   activating the first circuit in response to the clock signal to couple a first input signal to an output of the flip-flop circuit;   subsequently deactivating the first circuit and activating the second circuit in response to the clock signal to couple a second input signal to the output of the flip-flop circuit; and   delaying the clock signal to the first circuit, but not delaying the clock signal to the second circuit.   
     
     
         15 . The method of  claim 14 , wherein the first circuit comprises a first latch circuit and the second circuit comprises a second latch circuit. 
     
     
         16 . The method of a  claim 15 , wherein the the second latch circuit is coupled to the first latch circuit, and wherein in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the first and second input signals, respectively to the output signal. 
     
     
         17 . The method o  claim 16 , wherein the first and second latch circuits each comprises at most two transistors configured to receive the clock signal, wherein the first latch circuit includes a pair of cross-coupled OR-AND-Inverter (OAI) logic gates, and the second latch circuit includes a pair of cross-coupled AND-OR-Inverter (AOI) logic gates. 
     
     
         18 . The method of  claim 17 , wherein the at most two transistors of the first and second latch circuits, respectively, each receives the clock signal at a respective gate. 
     
     
         19 . The method of  claim 17 , wherein the at most two transistors of the first and second latch circuits, respectively, comprise a p-type metal-oxide-semiconductor transistor and an n-type metal-oxide-semiconductor transistor. 
     
     
         20 . The method of  claim 14 , further comprising:
 selecting either the first signal or the second signal to couple to the output in response to an enable signal.