Ferroelectric field-effect transistor devices having a top gate and a bottom gate

Abstract

Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) having a top gate and a bottom gate (or, generally, a dual-gate configuration). The disclosed FE-FET devices may be formed in the back end of the IC structure and may be implemented with various materials that exhibit ferroelectric properties when processed at temperatures within the thermal budget of the back-end processing. The disclosed back-end FE-FET devices can achieve greater than two resistance states, depending on the direction of poling of the top and bottom gates, thereby enabling the formation of 3-state and 4-state memory devices, for example. Additionally, as will be appreciated in light of this disclosure, the disclosed back-end FE-FET devices can free up floor space in the front-end, thereby providing space for additional devices in the front-end.

What is claimed is: 
     
         1 . An integrated circuit structure comprising:
 a first layer comprising a semiconductor material;   a first gate electrode on a first side of the first layer;   a second layer comprising a first ferroelectric material between the first gate electrode and the first layer;   a second gate electrode on a second side of the first layer; and   a third layer comprising a second ferroelectric material between the second gate electrode and the first layer, wherein the first gate electrode includes a first material having a first work function, and the second gate electrode includes a second material having a second work function, and the second work function of the second gate electrode material is at least 2.0 eV greater than or less than the first work function of the first gate electrode material.   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the wherein the second ferroelectric material of the third layer has a thickness of at least  5 nm greater than a thickness of the first ferroelectric material of the second layer. 
     
     
         3 . The integrated circuit structure of  claim 1 , wherein the wherein the first ferroelectric material of the second layer and the second ferroelectric material of the third layer comprise a same material. 
     
     
         4 . The integrated circuit structure of  claim 1 , wherein the wherein the first ferroelectric material of the second layer and the second ferroelectric material of the third layer comprise a different material. 
     
     
         5 . The integrated circuit structure of  claim 1 , wherein the semiconductor material of the first layer has a structure that is polycrystalline or amorphous. 
     
     
         6 . The integrated circuit structure of  claim 5 , wherein the semiconductor material of the first layer is selected from a group consisting of polycrystalline silicon, amorphous silicon, indium gallium zinc oxide (IGZO), a polycrystalline group III-V material, indium tin oxide (ITO), a complex oxide, and a transition metal dichalcogenide. 
     
     
         7 . An integrated circuit structure comprising:
 a middle layer comprising a semiconductor material;   a top layer comprising a first ferroelectric material above and in direct contact with the middle layer;   a bottom layer comprising a second ferroelectric material under and in direct contact the middle layer, wherein the first ferroelectric material and the second ferroelectric material have a polarization voltage difference of at least 25%.   
     
     
         8 . The integrated circuit structure of  claim 7 , further comprising:
 a top gate layer above the top layer; and   a bottom gate layer under the bottom layer.   
     
     
         9 . The integrated circuit structure of  claim 7 , wherein the wherein the second ferroelectric material has a thickness of at least  5 nm greater than a thickness of the first ferroelectric material. 
     
     
         10 . The integrated circuit structure of  claim 7 , wherein the wherein the first ferroelectric material has a thickness of at least  5 nm greater than a thickness of the second ferroelectric material. 
     
     
         11 . The integrated circuit structure of  claim 7 , wherein the wherein the first ferroelectric material and the second ferroelectric material comprise a same material. 
     
     
         12 . The integrated circuit structure of  claim 7 , wherein the wherein the first ferroelectric material and the second ferroelectric material comprise a different material. 
     
     
         13 . The integrated circuit structure of  claim 7 , wherein the semiconductor material of the middle layer has a structure that is polycrystalline or amorphous. 
     
     
         14 . The integrated circuit structure of  claim 13 , wherein the semiconductor material of the middle layer is selected from a group consisting of polycrystalline silicon, amorphous silicon, indium gallium zinc oxide (IGZO), a polycrystalline group III-V material, indium tin oxide (ITO), a complex oxide, and a transition metal dichalcogenide. 
     
     
         15 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including an integrated circuit structure, comprising:
 a first layer comprising a semiconductor material; 
 a first gate electrode on a first side of the first layer; 
 a second layer comprising a first ferroelectric material between the first gate electrode and the first layer; 
 a second gate electrode on a second side of the first layer; and 
 a third layer comprising a second ferroelectric material between the second gate electrode and the first layer, wherein the first gate electrode includes a first material having a first work function, and the second gate electrode includes a second material having a second work function, and the second work function of the second gate electrode material is at least 2.0 eV greater than or less than the first work function of the first gate electrode material. 
   
     
     
         16 . The computing device of  claim 15 , further comprising:
 a memory coupled to the board.   
     
     
         17 . The computing device of  claim 15 , further comprising:
 a communication chip coupled to the board.   
     
     
         18 . The computing device of  claim 15 , wherein the component is a packaged integrated circuit die. 
     
     
         19 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including an integrated circuit structure, comprising:
 a middle layer comprising a semiconductor material; 
 a top layer comprising a first ferroelectric material above and in direct contact with the middle layer; 
 a bottom layer comprising a second ferroelectric material under and in direct contact the middle layer, wherein the first ferroelectric material and the second ferroelectric material have a polarization voltage difference of at least  25 %. 
   
     
     
         20 . The computing device of  claim 19 , further comprising:
 a memory coupled to the board.   
     
     
         21 . The computing device of  claim 19 , further comprising:
 a communication chip coupled to the board.   
     
     
         22 . The computing device of  claim 19 , wherein the component is a packaged integrated circuit die.