Speculative side-channel attack mitigations

Abstract

Preventing the observation of the side effects of mispredicted speculative execution flows using speculation buffering. A microprocessor comprises one or more speculation buffers that are separated from and correspond to one or more conventional buffers. The microprocessor records first effects of one or more speculatively-executed instructions to the one or more speculation buffers, and records second effects of non-speculatively-executed instructions to the one or more conventional buffers. The microprocessor commits the first effects from the one or more speculation buffers to the one or more conventional buffers when the one or more speculatively-executed instructions that generated the first effects are committed, and discards the first effects from the one or more speculation buffers when the one or more speculatively-executed instructions are cancelled.

What is claimed: 
     
         1 . A microprocessor, comprising:
 one or more speculation buffers that are separated from and correspond to one or more conventional buffers;   first logic that records first effects of one or more speculatively-executed instructions to the one or more speculation buffers, and that records second effects of non-speculatively-executed instructions to the one or more conventional buffers; and   second logic that (i) commits the first effects from the one or more speculation buffers to the one or more conventional buffers when the one or more speculatively-executed instructions that generated the first effects are committed, and that (ii) discards the first effects from the one or more speculation buffers when the one or more speculatively-executed instructions are cancelled.   
     
     
         2 . The microprocessor of  claim 1 , wherein,
 the one or more speculation buffers comprise a speculative translation lookaside buffer (TLB), and the one or more conventional buffers comprise a TLB;   the first effects of the one or more speculatively-executed instructions comprise a memory address translation; and   committing the first effects from the one or more speculation buffers to the one or more conventional buffers comprises committing the memory address translation from the speculative TLB to the TLB.   
     
     
         3 . The microprocessor of  claim 1 , wherein,
 the one or more speculation buffers comprise a speculative data cache, and the one or more conventional buffers comprise a data cache;   the first effects of the one or more speculatively-executed instructions comprise a cache line; and   committing the first effects from the one or more speculation buffers to the one or more conventional buffers comprises committing the cache line from the speculative data cache to the data cache.   
     
     
         4 . The microprocessor of  claim 1 , wherein,
 the one or more speculation buffers comprise a speculative data cache;   the first logic fills the speculative data cache with a cache line from system memory, without filling an intermediary cache; and   committing the first effects comprises filling the intermediary cache with the cache line.   
     
     
         5 . The microprocessor of  claim 1 , wherein,
 the one or more speculation buffers comprise a speculative data cache;   the first logic fills the speculative data cache with a cache line from a first intermediary cache, without filling a second intermediary cache that is between the data cache and the first intermediary cache in a memory hierarchy; and   committing the first effects comprises filling the second intermediary cache with the cache line.   
     
     
         6 . The microprocessor of  claim 1 , wherein,
 the one or more speculation buffers comprise a speculative data cache corresponding to a first processing element;   the first logic fills the speculative data cache for a speculatively-executed instruction by employing a cache probe in accordance with a cache coherence protocol (CCP) to obtain data from a second processing element; and   the speculatively-executed instruction is held without filling the speculative data cache if the cache probe would result in a state change in a data cache of the second processing element.   
     
     
         7 . The microprocessor of  claim 1 , wherein a speculatively-executed instruction is held when a speculation buffer is full. 
     
     
         8 . The microprocessor of  claim 1 , wherein branch predictors are updated only with results from committed instructions. 
     
     
         9 . The microprocessor of  claim 1 , wherein the one or more speculation buffers include a first speculation buffer that is used by first speculatively-executed instructions from a first context, and a second speculation buffer that is used by second speculatively-executed instructions from a second context. 
     
     
         10 . The microprocessor of  claim 1 , wherein the first logic fills a speculation buffer entry based on execution of a first speculatively-executed instruction, and a second speculatively-executed instruction retrieves data from the speculation buffer entry prior to the first speculatively-executed instruction completing. 
     
     
         11 . The microprocessor of  claim 1 , wherein a speculatively-executed instruction causes invalidation of at least a portion of a specified cache line, and the invalidation is deferred until retiring of the speculatively-executed instruction. 
     
     
         12 . A method, implemented at a microprocessor that comprises one or more speculation buffers that are separated from and correspond to one or more conventional buffers, the method comprising:
 recording first effects of one or more speculatively-executed instructions to the one or more speculation buffers;   recording second effects of non-speculatively-executed instructions to the one or more conventional buffers;   committing the first effects from the one or more speculation buffers to the one or more conventional buffers when the one or more speculatively-executed instructions that generated the first effects are committed; and   discarding the first effects from the one or more speculation buffers when the one or more speculatively-executed instructions are cancelled.   
     
     
         13 . The method of  claim 12 , wherein,
 the one or more speculation buffers comprise a speculative translation lookaside buffer (TLB), and the one or more conventional buffers comprise a TLB;   the first effects of the one or more speculatively-executed instructions comprise a memory address translation; and   committing the first effects from the one or more speculation buffers to the one or more conventional buffers comprises committing the memory address translation from the speculative TLB to the TLB.   
     
     
         14 . The method of  claim 12 , wherein,
 the one or more speculation buffers comprise a speculative data cache, and the one or more conventional buffers comprise a data cache;   the first effects of the one or more speculatively-executed instructions comprise a cache line; and   committing the first effects from the one or more speculation buffers to the one or more conventional buffers comprises committing the cache line from the speculative data cache to the data cache.   
     
     
         15 . The method of  claim 12 , wherein,
 the one or more speculation buffers comprise a speculative data cache;   the method fills the speculative data cache with a cache line from system memory, without filling an intermediary cache; and   committing the first effects comprises filling the intermediary cache with the cache line.   
     
     
         16 . The method of  claim 12 , wherein,
 the one or more speculation buffers comprise a speculative data cache;   the method fills the speculative data cache with a cache line from a first intermediary cache, without filling a second intermediary cache that is between the data cache and the first intermediary cache in a memory hierarchy; and   committing the first effects comprises filling the second intermediary cache with the cache line.   
     
     
         17 . The method of  claim 12 , wherein,
 the one or more speculation buffers comprise a speculative data cache corresponding to a first processing element;   the method fills the speculative data cache for a speculatively-executed instruction by employing a cache probe in accordance with a cache coherence protocol (CCP) to obtain data from a second processing element; and   the speculatively-executed instruction is held without filling the speculative data cache if the cache probe would result in a state change in a data cache of the second processing element.   
     
     
         18 . The method of  claim 12 , wherein a speculatively-executed instruction is held when a speculation buffer is full. 
     
     
         19 . The method of  claim 12 , wherein branch predictors are updated only with results from committed instructions. 
     
     
         20 . A processing unit comprising one or more speculation buffers that are separated from and correspond to one or more conventional buffers, and control logic that configures the processing unit to:
 record first effects of one or more speculatively-executed instructions to the one or more speculation buffers;   record second effects of non-speculatively-executed instructions to the one or more conventional buffers;   commit the first effects from the one or more speculation buffers to the one or more conventional buffers when the one or more speculatively-executed instructions that generated the first effects are committed; and   discard the first effects from the one or more speculation buffers when the one or more speculatively-executed instructions are cancelled.