Microelectronic device and method for manufacturing such a device

Abstract

A device includes a MOS transistor and a bipolar transistor at a same first portion of a substrate. The first portion includes a first well doped with a first type forming the channel of the MOS transistor and two first regions doped with a second type opposite to the first type that are arranged in the first well which form the source and drain of the MOS transistor. The first portion further includes: a second well doped with the second type that is arranged laterally with respect to the first well to form the base of the bipolar transistor; a second region doped with the first type that is arranged in the second well to form the emitter of the bipolar transistor; and a third region doped with the first type that is arranged under the second well to form the collector of the bipolar transistor.

1 . A microelectronic device, comprising:
 a substrate;   a high-voltage MOS transistor in and/or on a first portion of said substrate; and   a bipolar transistor in and/or on the same first portion of said substrate;   wherein said first portion comprises:
 a first well doped with a first type that is electrically insulated from the substrate and configured to form a channel of the high-voltage MOS transistor; 
 two first regions doped with a second type opposite to the first type that are arranged in the first well and configured to form, respectively, a source and a drain of the high-voltage MOS transistor; 
 a second well doped with the second type that is arranged laterally with respect to the first well to form a base of the bipolar transistor; 
 a second region doped with the first type that is arranged in the second well to form an emitter of the bipolar transistor; and 
 a third region doped with the first type that is arranged under and in contact with the second well to form a collector of the bipolar transistor. 
   
     
     
         2 . The device according to  claim 1 , wherein said first portion further comprises:
 a fourth region doped with the second type that is arranged in the second well laterally with respect to the second region, said fourth region configured to form an electrical contact plug for the base of the bipolar transistor; and   an insulation region in the second well that laterally separates the fourth region from the second region.   
     
     
         3 . The device according to  claim 2 , wherein the insulation region is a shallow trench isolation having a depth that is deeper than a depth of the second region and deeper than a depth of the fourth region. 
     
     
         4 . The device according to  claim 2 , wherein said first portion further comprises:
 a third well doped with the first type that is arranged at a periphery of the second well and in electrical contact with the third region; and   a fifth region doped with the first type that is arranged in the third well;   wherein said fifth region and said third well are configured to form together an electrical contact plug for the collector of the bipolar transistor; and   a further insulation region in the second well that laterally separates the third well and the fifth region from the fourth region.   
     
     
         5 . The device according to  claim 4 , wherein the further insulation region is a shallow trench isolation having a depth that is deeper than a depth of the fifth region and deeper than a depth of the fourth region. 
     
     
         6 . The device according to  claim 1 , further comprising a low-voltage MOS transistor in a second portion of the substrate that is different from the first portion. 
     
     
         7 . The device according to  claim 6 , wherein the second portion comprises:
 a fourth well doped with the first type that is electrically insulated from the substrate and configured to form a channel of the low-voltage MOS transistor; and   two sixth regions doped with the second type that are arranged in the fourth well and configured to form, respectively, a source and a drain of the low-voltage MOS transistor;   wherein a doping of the first and second wells of the first portion is lower than a doping of the fourth well of the second portion.   
     
     
         8 . The device according to  claim 1 , wherein the bipolar transistor is of the NPN-type with the first doping type being an N-type doping and the second doping type being a P-type doping; and wherein the third region is an insulation well that is arranged between the first and second wells and the substrate. 
     
     
         9 . The device according to  claim 1 , wherein the bipolar transistor is of the PNP-type with the first doping type being a P-type doping and the second doping type being an N-type doping; and wherein the third region is a region of the substrate that is arranged under the second well. 
     
     
         10 . A method for manufacturing a microelectronic device comprising a high-voltage MOS transistor and a bipolar transistor formed in a same first portion of a substrate, said method comprising the following steps:
 (a) forming trenches in the substrate so as to define first and second active areas in the first portion;   (b) forming a first well doped with a first type in the first active area and a second well doped with a second type opposite to the first type in the second active area, wherein the first well forms a channel of the high-voltage MOS transistor and the second well forms a base of the bipolar transistor;   (c) forming two first regions doped with the second type that are arranged in the first well, wherein the two first regions form a source and a drain of the high-voltage MOS transistor;   (d) forming a second region doped with the first type that is arranged on the second well, wherein the second region forms an emitter of the bipolar transistor; and   (e) forming a third region doped with the first type that is arranged under and in contact with the second well to form a collector of the bipolar transistor.   
     
     
         11 . The method according to  claim 10 , wherein step (c) comprises:
 forming a fourth region doped with the second type that is arranged in the second well laterally with respect to the emitter, wherein said fourth region forms an electrical contact plug for the base of the bipolar transistor; and   forming an insulator that laterally separates the fourth region from the second region.   
     
     
         12 . The method according to  claim 10 , further comprising:
 forming a third well doped with the first type that is arranged at the periphery of the second well and in electrical contact with the third region; and   forming a fifth region doped with the first type that is arranged in the third well;   wherein said fifth region and said third well together form an electrical contact plug for the collector of the bipolar transistor.   
     
     
         13 . The method according to  claim 10 , wherein each step implements a single mask. 
     
     
         14 . The method according to  claim 10 , further comprising forming a low-voltage MOS transistor in a second portion of the substrate different from the first portion.