Systems and methods for hierarchical exposure of an integrated circuit having multiple interconnected die

Abstract

A system and method for fabricating distinct types of circuit connections on a semiconductor wafer includes fabricating, using a first photomask, a plurality of a first type of circuit connections for each of a plurality of distinct die of a semiconductor wafer; and fabricating, using a second photomask, a plurality of a second type of circuit connections between a plurality of distinct pairs of components of the semiconductor wafer, wherein each distinct pair of components includes at least one distinct die of the plurality of distinct die and one of a conductive pad and a sacrificial die.

We claim: 
     
         1 . A method comprising:
 fabricating a plurality of a first type of circuit connections for each of a plurality of distinct die within a first region of a semiconductor wafer; and   fabricating, using a photomask, a plurality of a second type of circuit connections between a plurality of distinct pairs of components of the semiconductor wafer,   wherein each second type of circuit connection comprises a first end supported by the first region and a coarse end supported by a sacrificial die within a peripheral region of the semiconductor wafer.   
     
     
         2 . The method of  claim 1 , wherein each distinct pair of components includes at least one distinct die of the plurality of distinct die and a conductive pad. 
     
     
         3 . The method of  claim 1 , wherein the sacrificial die comprises inactive die regions of the semiconductor wafer. 
     
     
         4 . The method of  claim 1 , wherein the fabrication using the photomask comprises:
 performing a single-shot exposure of the photomask to simultaneously create the plurality of the second type of circuit connections between each of the plurality of distinct pairs of components.   
     
     
         5 . The method according to  claim 1 , wherein:
 the plurality of distinct die of the semiconductor wafer includes a first set of die along a first peripheral boundary of the first region and a second set of die along a second peripheral boundary of the first region; and   the photomask comprises:
 a first circuit connection pattern for a first plurality of the second type of circuit connections along a first peripheral border of the photomask; and 
 a second circuit connection pattern for a second plurality of the second type of circuit connections along a second peripheral border of the photomask. 
   
     
     
         6 . The method of  claim 5 , wherein fabricating using the photomask further comprises:
 concurrently arranging the photomask over the first set of die and the second set of die of the semiconductor wafer; and   exposing the semiconductor wafer through the photomask to simultaneously transfer the first and second circuit connection patterns, respectively, to the first and second sets of die.   
     
     
         7 . The method of  claim 1 , further comprising:
 determining a number of functioning die of the plurality of distinct die within the first region,   wherein the fabrication of the plurality of the second type of circuit connections is based the number of functioning die satisfying a threshold.   
     
     
         8 . The method of  claim 1 , further comprising:
 after fabrication with the photomask, reducing a size of the semiconductor wafer, comprising severing a portion of each sacrificial die.   
     
     
         9 . The method of  claim 8 , wherein reducing size of the semiconductor further comprises:
 severing a second portion of the semiconductor along a boundary of the first region, the boundary arranged along a row of the first type circuit connections.   
     
     
         10 . The method of  claim 1 , wherein the plurality of the second type of circuit connections comprises fan-out circuit connections. 
     
     
         11 . The method of  claim 10 , wherein the fan-out connections are configured to establish communicative connectivity to an off-die circuit. 
     
     
         12 . The method of  claim 1 , wherein the sacrificial die supports a second coarse end of the circuit connection. 
     
     
         13 . The method of  claim 1 , wherein the second type of circuit connections are larger than the first type of circuit connections. 
     
     
         14 . The method of  claim 1 , wherein the first type of circuit connections comprises:
 a plurality of intra-die connections forming a circuit layer of each die; and   a plurality of inter-die connections that communicatively connect the circuit layer of each die to adjacent die of the plurality of distinct die within the first region.   
     
     
         15 . A method comprising:
 simultaneously fabricating a plurality of granular circuit connections for a plurality of distinct die of a semiconductor wafer, the plurality of distinct die comprising a first die; and   using a photomask, fabricating a plurality of coarse circuit connections between a plurality of distinct pairs of components of the semiconductor wafer, the plurality of distinct pairs of components comprising the first die and a conductive pad,   wherein the coarse circuit connections are larger than the granular circuit connections.   
     
     
         16 . The method of  claim 15 , wherein the fabrication using the photomask comprises:
 performing a single-shot exposure of the photomask to simultaneously create the plurality of coarse circuit connections between each of the plurality of distinct pairs of components.   
     
     
         17 . The method of  claim 15 , wherein the photomask comprises a circuit connection design that enables a fabrication of coarse circuit connections that extend between a first region of the semiconductor wafer which includes a plurality of active die and one or more second regions of the semiconductor wafer which comprise a plurality of inactive die regions that define a supporting substrate to one end of each coarse circuit connection. 
     
     
         18 . The method of  claim 17 , wherein:
 the coarse circuit connections comprise fan-out circuit connections, and   the plurality of inactive die regions support the fan-out circuit connections.   
     
     
         19 . The method according to  claim 15 , wherein:
 the plurality of distinct die of the semiconductor wafer includes a first set of die along a first peripheral boundary of an active die region of the semiconductor wafer and a second set of active die along a second peripheral boundary of the active die region of the semiconductor wafer; and   the photomask comprises:
 a first circuit connection pattern for a first plurality of the coarse circuit connections along a first peripheral border of the photomask; and 
 a second circuit connection pattern for a second plurality of the coarse circuit connections along a second peripheral border of the photomask. 
   
     
     
         20 . The method of  claim 1 , wherein the plurality of granular circuit connections comprises:
 a plurality of intra-die connections forming a circuit layer of each die; and   a plurality of inter-die connections that communicatively connect the circuit layer of each die to adjacent die of the plurality of distinct die.