US2021167034A1PendingUtilityA1
Chip arrangements
Est. expiryJun 7, 2031(~4.9 yrs left)· nominal 20-yr term from priority
Inventors:Manfred MengelAlexander HeinrichSteffen OrsoThomas BehrensOliver EichingerLim FongEvelyn NapetschnigEdmund Riedl
H10W 90/756H10W 90/736H10W 72/5525H10W 72/5522H10W 72/5363H10W 72/952H10W 72/951H10W 72/884H10W 72/552H10W 72/551H10W 72/536H10W 72/534H10W 72/352H10W 72/075H10W 72/073H10W 72/20H10W 70/417B23K 35/3013C22C 30/06C22C 18/04C22C 18/00B23K 35/262C22C 13/00B23K 1/0016C22C 30/04B23K 35/282H01L 2224/83H01L 2924/207H01L 2224/45099H01L 2224/48091H01L 2224/48465H01L 2924/01049H01L 2224/05599H01L 2224/45139H01L 2924/01047H01L 2924/01322H01L 2224/92247H01L 24/29H01L 2224/45014H01L 2224/45147H01L 24/83H01L 2224/45169H01L 23/49513H01L 2924/01032H01L 2924/00012H01L 2924/0103H01L 2924/0105H01L 2224/29139H01L 2224/32245H01L 2224/29111H01L 2924/00011H01L 2924/00014H01L 2924/01013H01L 2924/01029H01L 2924/15747H01L 2224/48247H01L 2924/10253H01L 24/73H01L 2224/73265H01L 2224/29118H01L 2224/45015H01L 2224/45144H01L 24/32H01L 23/488H01L 2224/45164H01L 24/48H01L 2224/85455H01L 2924/00H01L 2224/45155H01L 2924/01012
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Claims
Abstract
A chip arrangement including: a chip including a chip back side; a substrate including a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy including, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A chip arrangement comprising:
a chip comprising a chip back side; a substrate comprising a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy comprising, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.
2 . The chip arrangement of claim 1 , wherein the zinc-based solder alloy comprises by weight 3% to 8% aluminum.
3 . The chip arrangement of claim 1 , wherein the zinc-based solder alloy comprises by weight 0.5% to 4% germanium.
4 . The chip arrangement of claim 1 , wherein the zinc-based solder alloy comprises by weight 0.5% to 4% gallium.
5 . The chip arrangement of claim 1 , wherein the zinc-based solder alloy further comprises at least one from the following group of materials: silver, gold, nickel, platinum, palladium, vanadium, molybdenum, tin, copper, arsenic, antimony, niobium, tantalum, and/or any combination thereof, by weight 0.001% to 10% of the zinc-based solder alloy.
6 . The chip arrangement of claim 1 , wherein the plating comprises at least one of nickel or nickel-phosphorous.
7 . The chip arrangement of claim 6 , wherein the substrate comprises one or more of copper, nickel, silver, or ceramic.
8 . The chip arrangement of claim 7 , wherein the at least one of nickel or nickel-phosphorous in the plating provides a reduced void rate at an interface with the zinc-based solder alloy as compared to a void rate of the zinc-based solder alloy on the substrate without the plating.
9 . The chip arrangement of claim 1 , wherein the chip back side comprises a back side metallization comprising a plurality of layers, wherein a first layer of the plurality of layers is a contact layer which contacts a semiconductor material of the chip back side.
10 . The chip arrangement of claim 9 , wherein the contact layer comprises aluminum and has a thickness ranging from 50 nm to 1000 nm.
11 . The chip arrangement of claim 9 , wherein a second layer of the plurality of layers is a barrier layer comprising titanium or titanium-tungsten and has a thickness ranging from 50 nm to 1000 nm.
12 . The chip arrangement of claim 11 , wherein a third layer of the plurality of layers is a solder reaction layer comprising at least one of nickel, nickel-vanadium, silver, aluminum, gold, platinum, palladium, nickel, or combinations thereof, and has a thickness ranging from 50 nm to 1000 nm.
13 . The chip arrangement of claim 12 , wherein a fourth layer of the plurality of layers is an oxidation protection layer with a thickness ranging from 50 nm to 1000 nm.
14 . A chip arrangement comprising:
a chip comprising a chip back side; a substrate comprising a surface with a plating, wherein the plating comprises at least one of nickel or nickel-phosphorous; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy comprising, by weight, 1% to 20% aluminum, 1% to 20% magnesium, wherein a balance of the zinc-based solder alloy is zinc.
15 . The chip arrangement of claim 14 , wherein the zinc-based solder alloy comprises by weight 3% to 8% aluminum.
16 . The chip arrangement of claim 14 , wherein the zinc-based solder alloy comprises by weight 0.5% to 4% magnesium.
17 . The chip arrangement of claim 14 , wherein the zinc-based solder alloy further comprises at least one from the following group of materials: silver, gold, nickel, platinum, palladium, vanadium, molybdenum, tin, copper, arsenic, antimony, gallium, niobium, tantalum, and/or any combination thereof, by weight 0.001% to 10% of the zinc-based solder alloy.
18 . The chip arrangement of claim 14 , wherein the at least one of nickel or nickel-phosphorous in the plating provides a reduced void rate at an interface with the zinc-based solder alloy as compared to a void rate of the zinc-based solder alloy on the substrate without the plating.
19 . The chip arrangement of claim 18 , wherein the substrate comprises one or more of copper, nickel, silver, or ceramic.
20 . The chip arrangement of claim 19 , wherein the substrate comprises copper.Join the waitlist — get patent alerts
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