Sensing operations in memory

Abstract

The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array of memory cells and a second signal to a second portion of the array of memory cells.

What is claimed is: 
     
         1 . An apparatus, comprising:
 an array of memory cells; and   a controller configured to:
 perform sensing operations on the first portion of the array of memory cells using a first set of signals; and 
 perform sensing operations on the second portion of the array of memory cells using a second set of signals, wherein the first set of signals include magnitudes that are different than magnitudes of the second set of signals. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the controller is configured to partition the first portion and the second portion of the array of memory cells based on distance from a decoder of the apparatus. 
     
     
         3 . The apparatus of  claim 1 , wherein the controller is configured to partition the first portion and the second portion of the array of memory cells based on workload. 
     
     
         4 . The apparatus of  claim 1 , wherein the first portion and the second portion of the array of memory cells are managed with a different update technique. 
     
     
         5 . The apparatus of  claim 1 , where magnitudes of the first set of signals are based on a cycle count of the first portion of the array of memory cells and wherein magnitudes of the second set of signals are based on a cycle of the second portion of the array of memory cells. 
     
     
         6 . The apparatus of  claim 1 , wherein a first signal of first set of signals is applied to the first portion of the array of memory cells when the cycle count of the first portion of the array of memory cells is a first value and a first signal of the second set of signals is applied to the second portion of the array of memory cells when the cycle count of the second portion of the array of memory cells is the first value. 
     
     
         7 . The apparatus of  claim 6 , wherein a magnitude of the first signal of the first set of signals is different than a magnitude of the first signal of the second set of signals. 
     
     
         8 . An apparatus, comprising:
 an array of memory cells; and   a controller configured to:
 partition the array of memory cells into a first portion of the array of memory cells configured to store metadata and partition the array of memory cells into a second portion of the array of memory cells configured to store user data, wherein a cycle count of the first portion is monitored and a cycle count of the second portion is monitored; 
 perform sensing operations on the first portion of the array of memory cells using a first set of signals based on the cycle count of the first portion of the array of memory cells; and 
 perform sensing operations on the second portion of the array of memory cells using a second set of signals based on the cycle count of the second portion of the array of memory cells, wherein the first set of signals include magnitudes that are different than magnitudes of the second set of signals. 
   
     
     
         9 . The apparatus of  claim 8 , wherein the controller is configured to partition the array of memory cells at least partially based on a location of the first portion of the array of memory cells and a location of the second portion of the array of memory cells. 
     
     
         10 . The apparatus of  claim 8 , wherein the controller is configured to partition the array of memory cells at least partially based on a distance from a decoder of the apparatus to the first portion of the array of memory cells and a distance from the decoder of the apparatus to the second portion of the array of memory cells. 
     
     
         11 . The apparatus of  claim 8 , wherein the controller is configured to partition the array of memory cells into the first portion of the array of memory cells and the second portion of the array of memory cells at least partially based on type of data in the first portion of the array of memory cells and type of data in the second portion of the array of memory cells. 
     
     
         12 . The apparatus of  claim 8 , wherein the controller is configured to perform wear leveling on the array of memory cells by applying a first wear leveling scheme to the first portion of the array of memory cells to manage the cycle count of the first portion and a second wear leveling scheme to the second portion of the array of memory cells to manage the second cycle count of the second portion. 
     
     
         13 . The apparatus of  claim 8 , wherein the apparatus includes a first counter to monitor the cycle count of the first portion and a second counter to monitor the cycle count of the second portion. 
     
     
         14 . A method, comprising:
 performing sensing operations on an array of memory cells to identify a threshold voltage corresponding to a state of each memory cell in a first portion of the array of memory cells by applying a first set of signals to the first portion of the array of memory cells; and   performing sensing operations on an array of memory cells to identify a threshold voltage corresponding to a state of each memory cell in a second portion of the array of memory cells by applying a second set of signals to the second portion of the array of memory cells.   
     
     
         15 . The method  claim 14 , further comprising partitioning the array of memory cells into the first portion and the second portion based on workload of the array of memory cells. 
     
     
         16 . The method of  claim 14 , further comprising monitoring a cycle count of the first portion of the array of memory cells and monitoring a cycle count of the second portion of the array of memory cells. 
     
     
         17 . The method of  claim 14 , wherein each signal of the first set of signals corresponds to a range of cycle counts of the first portion of the array of memory cells. 
     
     
         18 . The method of  claim 17 , wherein each signal of the second set of signals corresponds to a range of cycle counts of the second portion of the array of memory cells. 
     
     
         19 . The method of  claim 18 , further including applying a first signal of the first set of signals to the first portion of the array of memory cells when a cycle count of the first portion is in a first range and applying a first signal of the second set of signals to the second portion of the array of memory cells when a cycle count of the second portion is in the first range. 
     
     
         20 . The method of  claim 14 , further comprising performing wear leveling on the array of memory cells by applying a first wear leveling scheme to the first portion of the array of memory cells to manage a cycle count of the first portion and a second wear leveling scheme to the second portion of the array of memory cells to manage a cycle count of the second portion.