Methods for forming multi-division staircase structure of three-dimensional memory device

Abstract

The disclosure provides a three-dimensional (3D) memory device. In an example, the 3D memory device includes a memory array structure and a staircase structure. The staircase structure includes a first staircase region including a first plurality of stairs. Each of the first plurality of stairs includes a first number of divisions at different depths in a first direction. The staircase structure also includes a second staircase region including a second plurality of stairs farther away from the memory array structure than the first plurality of stairs in a second direction perpendicular to the first direction. Each of the second plurality of stairs also includes the first number of the divisions. The staircase structure further includes at least one intermediate stair disposed between the first staircase region and the second staircase region in the second direction.

What is claimed is: 
     
         1 . A three-dimensional (3D) memory device, comprising:
 a memory array structure; and   a staircase structure, comprising:
 a first staircase region comprising a first plurality of stairs, wherein each of the first plurality of stairs comprises a first number of divisions at different depths in a first direction; 
 a second staircase region comprising a second plurality of stairs farther away from the memory array structure than the first plurality of stairs in a second direction perpendicular to the first direction, wherein each of the second plurality of stairs comprises the first number of the divisions; and 
 at least one intermediate stair between the first staircase region and the second staircase region in the second direction. 
   
     
     
         2 . The 3D memory device of  claim 1 , wherein each of the first staircase region and the second staircase region comprises at least two areas separated from one another in the first direction. 
     
     
         3 . The 3D memory device of  claim 2 , wherein the at least two areas in each of the first staircase region and the second staircase region have a same dimension in the first direction. 
     
     
         4 . The 3D memory device of  claim 2 , wherein the at least two areas in each of the first staircase region and the second staircase region have a same dimension in the second direction. 
     
     
         5 . The 3D memory device of  claim 2 , wherein a distance between two adjacent areas of the at least two areas in the first staircase region is the same as a distance between two adjacent areas of the at least two areas in the second staircase region. 
     
     
         6 . The 3D memory device of  claim 2 , wherein a distance between two adjacent areas of the at least two areas at a top stair in the first staircase region is the same as a distance between two adjacent areas of the at least two areas at a bottom stair in the first staircase region. 
     
     
         7 . The 3D memory device of  claim 2 , wherein a distance between two adjacent areas of the at least two areas at a top stair in the second staircase region is the same as a distance between two adjacent areas of the at least two areas at a bottom stair in the second staircase region. 
     
     
         8 . The 3D memory device of  claim 1 , wherein the staircase structure further comprises a peripheral region farther away from the memory array structure than the first staircase region in the second direction, the peripheral region comprising a third plurality of stairs without any divisions. 
     
     
         9 . The 3D memory device of  claim 1 , wherein a dimension of each of the at least one intermediate stair in the second direction is larger than a dimension of each of the first plurality of stairs and the second plurality of stairs in the second direction. 
     
     
         10 . The 3D memory device of  claim 1 , wherein the at least one intermediate stair comprises two intermediate stairs having a same number of divisions. 
     
     
         11 . The 3D memory device of  claim 1 , wherein the second staircase region abuts the first staircase region. 
     
     
         12 . The 3D memory device of  claim 11 , wherein the at least one intermediate stair comprises a second number of divisions in the first direction that is fewer than the first number of divisions included in the first staircase region and the second staircase region. 
     
     
         13 . The 3D memory device of  claim 1 , wherein the first staircase region and the second staircase region are overlapped in the second direction. 
     
     
         14 . The 3D memory device of  claim 13 , wherein the at least one intermediate stair comprises a second number of divisions in the first direction that is the same as the first number of divisions included in the first staircase region and the second staircase region. 
     
     
         15 . The 3D memory device of  claim 1 , wherein the first staircase region and the second staircase region are separated in the second direction. 
     
     
         16 . The 3D memory device of  claim 1 , wherein each two adjacent stairs among the first plurality of stairs are offset by a same distance in the second direction. 
     
     
         17 . The 3D memory device of  claim 1 , wherein each two adjacent stairs among the second plurality of stairs are offset by a same distance in the second direction.