Semiconductor Devices and Methods of Manufacture

Abstract

Semiconductor devices and methods of manufacture are provided wherein multiple integrated passive devices are integrated together utilizing an integrated fan out process in order to form a larger device with a smaller footprint. In particular embodiments the multiple integrated passive devices are capacitors which, once stacked together, can be utilized to provide a larger overall capacitance than any single passive device can obtain with a similar footprint.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first integrated passive device (IPD);   a first molding compound encapsulating the first IPD;   a redistribution structure over and electrically connected to the first IPD;   a second IPD on an opposing side of the redistribution structure as the first IPD, wherein the second IPD is electrically connected to the first IPD by the redistribution structure; and   a second molding compound encapsulating the second IPD.   
     
     
         2 . The semiconductor device of  claim 1 , wherein a face of the first IPD faces a face of the second IPD. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a face of the first IPD faces a back of the second IPD. 
     
     
         4 . The semiconductor device of  claim 1  further comprising a conductive via extending through the first molding compound. 
     
     
         5 . The semiconductor device of  claim 1  further comprising a conductive feature extending through the first molding compound, wherein the conductive feature comprises:
 a conductive via; and 
 a solder region on the conductive via. 
 
     
     
         6 . The semiconductor device of  claim 1 , wherein the first IPD is electrically connected to the redistribution structure by a copper pillar. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first IPD is electrically connected to the redistribution structure by a solder region. 
     
     
         8 . A semiconductor device comprising:
 a first redistribution structure;   a first functional die bonded to the first redistribution structure; and   a first integrated passive device stack bonded to the first redistribution structure, the first integrated passive device stack comprising:
 a second redistribution structure; 
 a first integrated passive device over the second redistribution structure; 
 a third redistribution structure over the first integrated passive device, the third redistribution structure being connected to the second redistribution structure by first through vias; and 
 a second integrated passive device over the third redistribution structure. 
   
     
     
         9 . The semiconductor device of  claim 8 , further comprising:
 a third integrated passive device between the second redistribution structure and the third redistribution structure; and   a first encapsulant surrounding the third integrated passive device and the first integrated passive device.   
     
     
         10 . The semiconductor device of  claim 8 , wherein the first through vias comprise copper pillars. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the first through vias comprise:
 copper pillars; and   solder balls in physical contact with the copper pillars.   
     
     
         12 . The semiconductor device of  claim 8 , wherein the first integrated passive device and the second integrated passive device are configured in a face-to-face configuration. 
     
     
         13 . The semiconductor device of  claim 8 , wherein the first integrated passive device and the second integrated passive device are configured in a back-to-face configuration. 
     
     
         14 . The semiconductor device of  claim 8 , wherein the first integrated passive device stack further comprises:
 a fourth redistribution structure over the second integrated passive device, the fourth redistribution structure being connected to the third redistribution structure by second through vias; and   a third integrated passive device over the fourth redistribution structure.   
     
     
         15 . A method of manufacturing a semiconductor device, the method comprising:
 forming a first redistribution structure over a carrier wafer;   forming through vias over the first redistribution structure;   placing a first integrated passive device on the first redistribution structure adjacent to the through vias;   encapsulating the first integrated passive device and the through vias with an encapsulant;   forming a second redistribution structure over the encapsulant and in electrical connection with the through vias; and   placing a second integrated passive device on the second redistribution structure and in electrical connection with the through vias.   
     
     
         16 . The method of  claim 15 , wherein the placing the first integrated passive device on the first redistribution structure places the first integrated passive device in electrical connection with the first redistribution structure. 
     
     
         17 . The method of  claim 15 , wherein the placing the first integrated passive device on the first redistribution structure utilizes an adhesive. 
     
     
         18 . The method of  claim 15 , wherein the placing the first integrated passive device places an integrated passive capacitor. 
     
     
         19 . The method of  claim 15 , further comprising bonding the first redistribution structure to a third redistribution layer. 
     
     
         20 . The method of  claim 19 , further comprising:
 bonding a first functional die to the third redistribution layer; and   encapsulating the first functional die in an encapsulant.