Methods and apparatus for an amplifier circuit

Abstract

Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may be utilized in a digital-to-analog converter. The amplifier circuit may comprise a first operational amplifier with a feedback circuit. The feedback circuit may comprise an inverting amplifier circuit.

1 . An integrated circuit, comprising:
 a first amplifier comprising:
 a non-inverting input terminal; and 
 an output terminal; and 
   a inverting amplifier circuit connected to the first amplifier and comprising:
 a second amplifier comprising:
 an inverting input terminal connected to the output terminal of the first amplifier; and 
 an output terminal connected to the non-inverting terminal of the first amplifier. 
 
   
     
     
         2 . The integrated circuit according to  claim 1 , wherein the inverting amplifier circuit further comprises at least one of a first resistor and a first capacitor, wherein the at least one of the resistor and the capacitor is connected between the output terminal of the second amplifier and the inverting terminal of the second amplifier. 
     
     
         3 . The integrated circuit according to  claim 1 , further comprising an RC circuit connected between the output terminal of the second amplifier and the non-inverting terminal of the first amplifier; 
     
     
         4 . The integrated circuit according to  claim 3 , wherein the RC comprises a resistor and a capacitor are connected in parallel with each other. 
     
     
         5 . The integrated circuit according to  claim 1 , wherein the second amplifier further comprises a non-inverting input terminal connected to a reference voltage. 
     
     
         6 . The integrated circuit according to  claim 1 , further comprising a second resistor connected directly between the output terminal of the first amplifier and the inverting terminal of the second amplifier. 
     
     
         7 . The integrated circuit according to  claim 1 , further comprising:
 a second resistor connected to the output terminal of the second amplifier; and   a second capacitor connected to the output terminal of the second amplifier and the non-inverting terminal of the first amplifier;   wherein the second resistor is further connected to:
 the inverting terminal of the first amplifier via a third capacitor and a third resistor; and 
 the non-inverting terminal of the first amplifier via a fourth resistor. 
   
     
     
         8 . The integrated circuit according to  claim 1 , wherein the integrated circuit is configured to:
 receive differential input signals; and   generate a single-ended output.   
     
     
         9 . A method, comprising:
 receiving, at a first amplifier, a differential signal comprising a first input signal and a second input signal, wherein the first input signal is received at a first terminal of the first amplifier and the second input signal is received at a second terminal of the first amplifier;   generating, with the first amplifier, a first output signal according to the differential signal;   transmitting the first output signal to a first terminal of a second amplifier;   generating, with the second amplifier, a second output signal according to the first output signal; and   transmitting the second output signal to the second terminal of the first amplifier.   
     
     
         10 . The method according to  claim 9 , further comprising generating a first feedback signal according to the first output signal and applying the first feedback signal to the first input terminal of the first amplifier. 
     
     
         11 . The method according to  claim 9 , further comprising generating a second feedback signal according to the second output signal and applying the second feedback signal to the first input terminal of the second amplifier. 
     
     
         12 . The method according to  claim 9 , the amplitude of the first input signal is substantially zero and the amplitude of the second input signal is substantially zero. 
     
     
         13 . A system configured to receive an input signal, comprising:
 a digital circuit configured to generate a multi-bit digital signal based on the input signal; and   an analog circuit connected to the digital circuit and comprising:
 an output buffer comprising:
 a first amplifier comprising:
 a non-inverting input terminal; and 
 a first output terminal; 
 
 a second amplifier comprising:
 an inverting input terminal connected to the output terminal of the first amplifier; and 
 a second output terminal connected to the non-inverting terminal of the first amplifier; and 
 
 an RC circuit connected between the second output terminal of the second amplifier and the non-inverting input terminal of the first amplifier. 
 
   
     
     
         14 . The system according to  claim 13 , wherein the output buffer further comprises:
 a first resistor connected between the second output terminal of the second amplifier and the inverting terminal of the second amplifier; and   a first capacitor connected between the second output terminal of the second amplifier and the inverting terminal of the second amplifier, wherein the capacitor is connected in parallel with the first resistor.   
     
     
         15 . The system according to  claim 13 , wherein the RC circuit comprises a resistor and a capacitor connected in parallel with each other; wherein the resistor and the capacitor are connected directly between the output terminal of the second amplifier and the non-inverting terminal of the first amplifier. 
     
     
         16 . The system according to  claim 13 , wherein the second amplifier further comprises a non-inverting input terminal connected to a reference voltage. 
     
     
         17 . The system according to  claim 13 , further comprising a second resistor connected directly between the first output terminal of the first amplifier and the inverting terminal of the second amplifier. 
     
     
         18 . The system according to  claim 13 , further comprising:
 a second resistor connected between the output terminal of the first amplifier and the inverting terminal of the first amplifier; and   a second capacitor connected between the output terminal of the first amplifier and the inverting terminal of the first amplifier, wherein the second capacitor is connected in parallel with the second resistor.   
     
     
         19 . The system according to  claim 13 , further comprising:
 a second resistor connected to the second output terminal of the second amplifier; and   a second capacitor connected to the second output terminal of the second amplifier and the non-inverting terminal of the first amplifier;   wherein the second resistor is further connected to:
 the inverting terminal of the first amplifier via a third capacitor and a third resistor; and 
 the non-inverting terminal of the first amplifier via a fourth resistor. 
   
     
     
         20 . The system according to  claim 13 , wherein the integrated circuit is configured to:
 receive differential input signals; and   generate a single-ended output.