Semiconductor device and method for fabricating the same

Abstract

A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.

What is claimed is: 
     
         1 . A method for fabricating semiconductor device, comprising:
 forming a magnetic tunneling junction (MTJ) stack on a substrate;   forming a top electrode on the MTJ stack;   performing a first patterning process to remove the MTJ stack along a first direction; and   performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a bottom electrode on the substrate;   forming the MTJ stack on the bottom electrode;   forming a stop layer on the MTJ stack;   forming the top electrode on the stop layer; and   forming a hard mask on the top electrode.   
     
     
         3 . The method of  claim 2 , wherein the first patterning process comprises removing the hard mask and the top electrode along the first direction. 
     
     
         4 . The method of  claim 3 , wherein the second patterning process comprises:
 performing a first etching process to remove the hard mask and the top electrode along the second direction; and   performing a second etching process to remove the etch stop layer, the MTJ stack, and the bottom electrode to form MTJs.   
     
     
         5 . The method of  claim 1 , wherein the first direction is orthogonal to the second direction. 
     
     
         6 . A semiconductor device, comprising:
 a magnetic tunneling junction (MTJ) on a substrate, wherein a top view of the MTJ comprises at least one corner and the at least one corner is less than 90 degrees.   
     
     
         7 . The semiconductor device of  claim 6 , further comprising:
 an inter-metal dielectric (IMD) layer on the substrate and around the MTJ; and   a top electrode on the MTJ.   
     
     
         8 . The semiconductor device of  claim 7 , wherein a top view of the top electrode comprises a quadrilateral. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the quadrilateral comprises two corners and each of the two corners is less than 90 degrees. 
     
     
         10 . The semiconductor device of  claim 8 , wherein the quadrilateral comprises three corners and each of the three corners is less than 90 degrees. 
     
     
         11 . The semiconductor device of  claim 8 , wherein the quadrilateral comprises four corners and each of the four corners is less than 90 degrees. 
     
     
         12 . The semiconductor device of  claim 8 , wherein the quadrilateral comprises:
 a first side and a second side extending along a first direction;   a third side connecting the first side and the second side; and   a fourth side connecting the first side and the second side.   
     
     
         13 . The semiconductor device of  claim 12 , wherein each of the third side and the fourth side comprises a curve. 
     
     
         14 . The semiconductor device of  claim 13 , wherein each of the third side and the fourth side comprises a concave curve. 
     
     
         15 . The semiconductor device of  claim 7 , wherein a top view of the top electrode comprises a hexagon. 
     
     
         16 . The semiconductor device of  claim 15 , wherein the hexagon comprises two corners and each of the two corners is less than 90 degrees. 
     
     
         17 . The semiconductor device of  claim 15 , wherein the hexagon comprises three corners and each of the three corners is less than 90 degrees. 
     
     
         18 . The semiconductor device of  claim 15 , wherein the hexagon comprises four corners and each of the four corners is less than 90 degrees. 
     
     
         19 . The semiconductor device of  claim 15 , wherein the hexagon comprises:
 a first side and a second side extending along a first direction;   a third side connecting the first side and the second side; and   a fourth side connecting the first side and the second side.   
     
     
         20 . The semiconductor device of  claim 19 , wherein each of the third side and the fourth side comprises a V-shape.