Semiconductor structure and fabrication method thereof

Abstract

A semiconductor structure is provided. The semiconductor structure includes a gate structure on a base substrate; a first stress layer in the base substrate on both sides of the gate structure; and a second stress layer in the first stress layer and surrounded by the first stress layer. The doping concentration of the second stress layer is greater than or equal to a doping concentration of the first stress layer.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a gate structure on a base substrate;   a first stress layer in the base substrate on both sides of the gate structure; and   a second stress layer in the first stress layer and surrounded by the first stress layer wherein a doping concentration of the second stress layer is greater than or equal to a doping concentration of the first stress layer.   
     
     
         2 . The semiconductor structure according to  claim 1 , wherein:
 the second stress layer is made of one of silicon germanium, and silicon carbon.   
     
     
         3 . The semiconductor structure according to  claim 1 , wherein:
 the first stress layer is in contact with a sidewall spacer of the gate structure.   
     
     
         4 . The semiconductor structure according to  claim 1 , wherein:
 the first stress layer is made of one of silicon germanium and silicon;   the second stress layer is made of silicon germanium; and   a content of germanium in the second stress layer is greater than or equal to a content of germanium in the first stress layer.   
     
     
         5 . The semiconductor structure according to  claim 1 , wherein:
 the first stress layer is made of one of silicon carbon and silicon;   the second stress layer is made of silicon carbon; and   a content of carbon in the second stress layer is greater than or equal to a content of carbon in the first stress layer.   
     
     
         6 . The semiconductor structure according to  claim 1 , wherein:
 the gate structure is a metal gate structure.   
     
     
         7 . The semiconductor structure according to  claim 1 , further including:
 an interlayer dielectric layer formed on the base substrate, wherein the interlayer dielectric layer has contact holes on two sides of the gate structure and a bottom of each contact hole exposes the first stress layer, and   a plug formed in each contact hole.   
     
     
         8 . The semiconductor structure according to  claim 1 , wherein:
 the second stress layer has a top surface coplanar with a top surface of the first stress layer, and the second stress layer is completely covered by the first stress layer from a bottom surface and side surfaces of the second stress layer.   
     
     
         9 . The semiconductor structure according to  claim 1 , wherein:
 the semiconductor structure is a PMOS,   in-situ self-doped dopant ions are B ions, and   a doping concentration of the second stress layer is in a range of approximately 2.0×10 20  atoms/cm 3 -1.5×10 21  atoms/cm 3 .   
     
     
         10 . The semiconductor structure according to  claim 1 , wherein:
 the semiconductor structure is an NMOS,   in-situ self-doped dopant ions are P ions, and   a doping concentration of the second stress layer is in a range of approximately 8.0×10 20  atoms/cm 3 -2.5×10 21  atoms/cm 3 .   
     
     
         11 . The semiconductor structure according to  claim 1 , further including:
 an anti-leakage doped region in the base substrate under the first stress layer.