Nanosheet devices with improved electrostatic integrity

Abstract

Semiconductor devices include channel structures, arranged in vertically aligned pairs of channel structures. A gate stack is formed around all of the plurality of channel structures, filling a space between each pair of channel structures. Inner spacers are formed at respective ends of the channel structures, each having a vertical central portion and horizontal portions that extend outward from sides of the central portion, between the channels.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a plurality of channel structures, arranged in vertically aligned pairs of channel structures;   a gate stack formed around all of the plurality of channel structures, filling a space between each pair of channel structures; and   inner spacers formed at respective ends of the channel structures, each having a vertical central portion and a plurality of horizontal portions that extend outward from sides of the central portion, between the channels.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising a bottom dielectric layer formed between the gate stack and an underlying substrate. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the bottom dielectric layer comprises a continuous layer of material that shares a footprint with the vertically aligned pairs of channel structures. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a width of the space between the channel structures in each pair of channel structures is 10 nm or less. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a substrate that has plateau in a region directly under the plurality of channel structures. 
     
     
         6 . The semiconductor device of  claim 5 , further comprising source and drain structures that have a width greater than a width of the plateau. 
     
     
         7 . The semiconductor device of  claim 5 , further comprising a bottom dielectric layer that is between the gate stack and the substrate, in an area around the plateau. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the gate stack is a gate-all-around structure that surrounds each of the plurality of channel structures. 
     
     
         9 . A semiconductor device, comprising:
 a substrate having a plateau;   a plurality of channel structures directly over the plateau, arranged in vertically aligned pairs of channel structures;   a gate stack formed around all of the plurality of channel structures, filling a space between each pair of channel structures; and   inner spacers formed at respective ends of the channel structures, each having a vertical central portion and a plurality of horizontal portions that extend outward from sides of the central portion, between the channels.   
     
     
         10 . The semiconductor device of  claim 9 , further comprising a bottom dielectric layer formed between the gate stack and the substrate. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the bottom dielectric layer comprises a continuous layer of material that shares a footprint with the vertically aligned pairs of channel structures. 
     
     
         12 . The semiconductor device of  claim 9 , wherein a width of the space between the channel structures in each pair of channel structures is 10 nm or less. 
     
     
         13 . The semiconductor device of  claim 9 , further comprising source and drain structures that have a width greater than a width of the plateau. 
     
     
         14 . The semiconductor device of  claim 9 , further comprising a bottom dielectric layer that is between the gate stack and the substrate, in an area around the plateau. 
     
     
         15 . The semiconductor device of  claim 9 , wherein the gate stack is a gate-all-around structure that surrounds each of the plurality of channel structures. 
     
     
         16 . A semiconductor device, comprising:
 a substrate having a plateau;   a first bottom dielectric layer directly over the plateau;   a plurality of channel structures, arranged in vertically aligned pairs of channel structures;   a gate stack formed around all of the plurality of channel structures, directly over the first bottom dielectric layer, filling a space between each pair of channel structures; and   inner spacers formed at respective ends of the channel structures, each having a vertical central portion and a plurality of horizontal portions that extend outward from sides of the central portion, between the channels; and   source and drain structures that have a width greater than a width of the plateau.   
     
     
         17 . The semiconductor device of  claim 16 , wherein the bottom dielectric layer comprises a continuous layer of material that shares a footprint with the vertically aligned pairs of channel structures. 
     
     
         18 . The semiconductor device of  claim 16 , wherein a width of the space between the channel structures in each pair of channel structures is 10 nm or less. 
     
     
         19 . The semiconductor device of  claim 16 , further comprising a second bottom dielectric layer that is between the gate stack and the substrate, in an area around the plateau. 
     
     
         20 . The semiconductor device of  claim 16 , wherein the gate stack is a gate-all-around structure that surrounds each of the plurality of channel structures.