Semiconductor device, and method for manufacturing semiconductor device

Abstract

There is provided a reverse-blocking semiconductor device that has a simple configuration, that is capable of improving a yield in a manufacturing process, and that secures a reverse withstand voltage by using a Schottky junction, and there is provided a method for manufacturing the reverse-blocking semiconductor device. A semiconductor device is provided that includes a first conductivity type semiconductor layer that has a front surface, a rear surface on an opposite side of the front surface, and an end surface, a MIS transistor structure formed at a front-surface portion of the semiconductor layer, a first electrode that forms a Schottky junction with a part of the semiconductor layer in the rear surface of the semiconductor layer, and an electric-field relaxation region that is formed to reach the rear surface from the front surface of the semiconductor layer in a peripheral region surrounding an active region in which the MIS transistor structure is formed and that is either a high-resistance region having higher resistance than the semiconductor layer or a second conductivity type impurity region.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor layer of a first conductivity type that has a front surface, a rear surface on an opposite side of the front surface, and an end surface, the semiconductor layer having an active region and a peripheral region surrounding the active region;   a circuit element formed at a front-surface portion of the semiconductor layer in the active region; and   a first electrode that is joined to the semiconductor layer in the rear surface of the semiconductor layer,   the first electrode being in contact with a part of the semiconductor layer in the rear surface of the semiconductor layer such that the first electrode forms a Schottky junction with the part of the semiconductor layer.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising an electric-field relaxation region reaching the rear surface from the front surface of the semiconductor layer in the peripheral region, the electric-field relaxation region being at least one of a high-resistance region having higher resistance than the semiconductor layer and a second conductivity type impurity region. 
     
     
         3 . The semiconductor device according to  claim 2 , wherein the electric-field relaxation region is formed inwardly away from the end surface of the semiconductor layer such that the electric-field relaxation region surrounds the active region. 
     
     
         4 . The semiconductor device according to  claim 3 , further comprising a peripheral impurity region of a first conductivity type formed between the electric-field relaxation region and the end surface of the semiconductor layer. 
     
     
         5 . The semiconductor device according to  claim 4 , wherein the first electrode forms a Schottky junction with the part of the semiconductor layer and the peripheral impurity region. 
     
     
         6 . The semiconductor device according to  claim 2 , wherein the semiconductor layer is SiC, and the electric-field relaxation region is a high-resistance region having a crystal defect concentration of 1×10 14  cm −3  to 1×10 22  cm −3 . 
     
     
         7 . The semiconductor device according to  claim 2 , wherein the semiconductor layer is SiC, and the electric-field relaxation region is a second conductivity type impurity region having an impurity concentration of 1×10 18  cm −3  to 1×10 22  cm −3 . 
     
     
         8 . The semiconductor device according to  claim 5 ,
 wherein the semiconductor device further comprising an auxiliary electrode that is in contact with the peripheral impurity region in the front surface of the semiconductor layer and that is electrically connected to the first electrode.   
     
     
         9 . The semiconductor device according to  claim 8 , wherein the auxiliary electrode straddles a boundary portion between the electric-field relaxation region and the peripheral impurity region, and is in contact with both the electric-field relaxation region and the peripheral impurity region. 
     
     
         10 . The semiconductor device according to  claim 2 , wherein the electric-field relaxation region reaches the end surface of the semiconductor layer. 
     
     
         11 . The semiconductor device according to  claim 2 , wherein the first electrode is in contact with the electric-field relaxation region in the rear surface of the semiconductor layer,
 the semiconductor device further comprising an auxiliary electrode that is in contact with the electric-field relaxation region in the front surface of the semiconductor layer and that is electrically connected to the first electrode.   
     
     
         12 . The semiconductor device according to  claim 1 ,
 wherein a MIS transistor structure serving as the circuit element is formed at the front-surface portion of the semiconductor layer.   
     
     
         13 . The semiconductor device according to  claim 2 , wherein the peripheral region of the semiconductor layer includes a flat portion with which the front surface of the semiconductor layer is flat, and
 wherein the electric-field relaxation region reaches the rear surface from the front surface of the semiconductor layer of the flat portion.   
     
     
         14 . The semiconductor device according to  claim 2  further comprising a concave portion formed from the front surface in the peripheral region of the semiconductor layer,
 wherein the electric-field relaxation region is formed along an inner surface of the concave portion, and has a bottom portion exposed at the rear surface of the semiconductor layer. 
 
     
     
         15 . The semiconductor device according to  claim 1 , further comprising a second electric-field relaxation region that is formed at a rear-surface portion of the semiconductor layer and that is at least one of a high-resistance region having higher resistance than the semiconductor layer and a second conductivity type impurity region. 
     
     
         16 . The semiconductor device according to  claim 15 , wherein the second electric-field relaxation region is exposed to the rear surface of the semiconductor layer, and
 wherein the first electrode is in contact with the second electric-field relaxation region in the rear surface of the semiconductor layer.   
     
     
         17 . The semiconductor device according to  claim 15 , wherein a plurality of the second electric-field relaxation regions are arranged in a discrete and matrix manner when the semiconductor layer is seen from a side of the rear surface. 
     
     
         18 . The semiconductor device according to  claim 15 , wherein a plurality of the second electric-field relaxation regions are arranged in at least one of a stripe manner or formed in a grid pattern manner when the semiconductor layer is seen from a side of the rear surface. 
     
     
         19 . The semiconductor device according to  claim 2 , further comprising a surface termination structure formed on a more inward side than the electric-field relaxation region in the peripheral region of the semiconductor layer. 
     
     
         20 . The semiconductor device according to  claim 12 , further comprising a second electrode that is formed on the semiconductor layer and that is electrically connected to at least one of a source or an emitter of the MIS transistor structure.