Semiconductor die with buried capacitor, and method of manufacturing the semiconductor die

Abstract

A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

1 . A method of manufacturing an integrated circuit, comprising:
 forming a buried cavity in a semiconductor body;   etching selective portions of the semiconductor body located over the buried cavity until the buried cavity is reached to form one or more openings which have access to the buried cavity;   depositing dielectric material through the one or more openings so as to completely coat inner walls of the buried cavity to form a dielectric layer; and   depositing conductive material through the one or more openings so as to completely coat the dielectric layer within the buried cavity and form a first layer of conductive material;   wherein said first layer of conductive material forms a first plate of a capacitor buried in the semiconductor body and the dielectric layer provides a dielectric of said capacitor.   
     
     
         2 . The method according to  claim 1 , wherein said semiconductor body forms a second plate of said capacitor, with the dielectric layer arranged between the first and second plates of said capacitor. 
     
     
         3 . The method according to  claim 1 , wherein the depositing dielectric material comprises carrying out a respective deposition using one of a CVD technology or an ALD technology. 
     
     
         4 . The method according to  claim 1 , wherein the depositing conductive material comprises carrying out a respective deposition using one of a CVD technology or an ALD technology. 
     
     
         5 . The method according to  claim 1 , wherein depositing conductive material comprises sealing said one or more openings closed with the deposited conductive material. 
     
     
         6 . The method according to  claim 5 , wherein sealing further comprises leaving a hollow portion within the deposited conductive material. 
     
     
         7 . A method of manufacturing an integrated circuit, comprising:
 forming a buried cavity in a semiconductor body;   etching selective portions of the semiconductor body located over the buried cavity until the buried cavity is reached to form one or more openings which have access to the buried cavity;   forming an insulating layer within the buried cavity by one of a deposition or a thermal growth so as to completely coat inner walls of the buried cavity;   depositing first conductive material through the one or more openings so as to completely coat the insulating layer within the buried cavity and form a first layer of conductive material;   depositing a layer of dielectric material through the one or more openings so as to completely cover the first layer of conductive material within the buried cavity and form a dielectric layer; and   depositing second conductive material through the one or more openings in order to completely coat the dielectric layer within the buried cavity and form a second layer of conductive material;   wherein said first layer of conductive material forms a first plate of a capacitor buried in the semiconductor body, the dielectric layer provides a dielectric of said capacitor and said second layer of conductive material forms a second plate of a capacitor buried in the semiconductor body.   
     
     
         8 . The method according to  claim 7 , wherein depositing the layer of dielectric material includes carrying out a deposition using one of a CVD technology or an ALD technology. 
     
     
         9 . The method according to  claim 7 , wherein depositing conductive material includes carrying out a deposition using one of a CVD technology or an ALD technology. 
     
     
         10 . The method according to  claim 7 , wherein depositing second conductive material comprises sealing said one or more openings closed with the deposited conductive material. 
     
     
         11 . The method according to  claim 10 , wherein sealing further comprises leaving a hollow portion within the deposited conductive material.