Embedded non-volatile memory device and fabrication method of the same

Abstract

Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device, comprising:
 a memory cell in a first region of a substrate, the memory cell including a polysilicon memory gate (MG) overlying a charge trapping layer; and   a logic field-effect transistor (FET) including a metal gate disposed over a high-k dielectric in a second region of the substrate,   wherein the MG of the memory cell and the metal gate of the logic FET have substantially a same height.   
     
     
         22 . The semiconductor device of  claim 21  wherein the memory cell is a split-gate memory cell further comprising a polysilicon select gate (SG) overlying a SG oxide layer, the SG formed adjacent to the MG and separated therefrom by an inter-gate dielectric. 
     
     
         23 . The semiconductor device of  claim 22  wherein top surfaces of the MG, the SG and the metal gate of the logic FET are substantially co-planar. 
     
     
         24 . The semiconductor device of  claim 23  wherein a first surface of the substrate in the first region and a second surface of the substrate in the second region of the substrate are substantially co-planar. 
     
     
         25 . The semiconductor device of  claim 23  wherein the inter-gate dielectric extends from the SG oxide layer to the top surfaces of the MG and the SG. 
     
     
         26 . The semiconductor device of  claim 23  wherein the top surface of at least one of the MG and the SG is silicided. 
     
     
         27 . The semiconductor device of  claim 23  wherein the top surfaces of the MG and the SG are silicided, and wherein no silicide lies above the inter-gate dielectric that separates the SG and the MG. 
     
     
         28 . The semiconductor device of  claim 22  further comprising an inter-layer dielectric (ILD) formed over the substrate surrounding the MG, the SG and the metal gate of the logic FET, the ILD planarized to have a top surface substantially co-planar with the top surfaces of the MG, the SG and the metal gate of the logic FET. 
     
     
         29 . The semiconductor device of  claim 22  wherein the charge trapping layer is a multi-layer charge trapping layer comprising an oxide-nitride-oxide (ONO) stack, and wherein a lower oxide of the ONO stack is formed from an oxide layer that is contiguous with the SG oxide layer. 
     
     
         30 . A semiconductor device, comprising:
 a plurality of split-gate memory cells in a memory region of a substrate, each split gate memory cell including a polysilicon memory gate (MG) overlying a charge trapping layer, and a polysilicon select gate (SG) overlying a SG oxide layer formed adjacent to the MG and separated therefrom by an inter-gate dielectric; and   a plurality of logic field-effect transistor (FET) in a logic region of the substrate, each logic FET including a metal gate disposed over a high-k dielectric,   wherein top surfaces of each of the MGs, the SGs and the metal gate of the logic FETs are substantially co-planar.   
     
     
         31 . The semiconductor device of  claim 30  wherein the inter-gate dielectric in each split gate memory cell extends from the SG oxide layer to the top surfaces of the MG and the SG. 
     
     
         32 . The semiconductor device of  claim 30  wherein the top surfaces of each of the MG and the SG are silicided, and wherein no silicide lies above the inter-gate dielectric that separates the SG and the MG in at least one of the split-gate memory cell. 
     
     
         33 . The semiconductor device of  claim 30  further comprising an inter-layer dielectric (ILD) formed over the substrate surrounding the MGs, the SGs and the metal gate of the logic FETs, the ILD planarized to have a top surface substantially co-planar with the top surfaces of the MGs, the SGs and the metal gate of the logic FETs. 
     
     
         34 . The semiconductor device of  claim 30  wherein the charge trapping layer in each split gate memory cell is a multi-layer charge trapping layer comprising an oxide-nitride-oxide (ONO) stack, and wherein a lower oxide of the ONO stack is formed from an oxide layer that is contiguous with the SG oxide layer. 
     
     
         35 . A semiconductor device, comprising:
 a memory array including a plurality of split-gate devices in a memory region of a substrate, each split-gate device including a polysilicon memory gate (MG) overlying a charge trapping layer, and a polysilicon select gate (SG) overlying a SG oxide layer formed adjacent to the MG and separated therefrom by an inter-gate dielectric; and   control circuitry including a plurality of logic field-effect transistor (FET) in a logic region of the substrate, each logic FET including a metal gate disposed over a high-k dielectric,   wherein top surfaces of each of the MGs, the SGs and the metal gate of the logic FETs are substantially co-planar.   
     
     
         36 . The semiconductor device of  claim 35  wherein the inter-gate dielectric in each split gate memory cell extends from the SG oxide layer to the top surfaces of the MG and the SG. 
     
     
         37 . The semiconductor device of  claim 35  wherein the top surfaces of each of the MG and the SG are silicided, and wherein no silicide lies above the inter-gate dielectric that separates the SG and the MG in each split-gate memory cell. 
     
     
         38 . The semiconductor device of  claim 35  further comprising an inter-layer dielectric (ILD) formed over the substrate surrounding the MGs, the SGs and the metal gate of the logic FETs, the ILD planarized to have a top surface substantially co-planar with the top surfaces of the MGs, the SGs and the metal gate of the logic FETs. 
     
     
         39 . The semiconductor device of  claim 35  wherein the charge trapping layer in each split gate memory cell is a multi-layer charge trapping layer comprising an oxide-nitride-oxide (ONO) stack, and wherein a lower oxide of the ONO stack is formed from an oxide layer that is contiguous with the SG oxide layer. 
     
     
         40 . The semiconductor device of  claim 35  wherein the control circuitry comprises row and column decoders, sense amplifiers and word line or bit line drivers used to the address plurality of split-gate devices in the memory array.