Hybrid integrated semiconductor tri-gate and split dual-gate finfet devices

Abstract

An integrated circuit apparatus includes a silicon-on-insulator (SOI) substrate comprising a silicon layer overlying an insulator layer; a first silicon fin region formed in a first region of the silicon layer, the first silicon fin region comprising a first source region, a first drain region, and a first channel region; a second silicon fin region formed in a second region of the silicon layer, the second silicon fin region comprising a second source region, a second drain region, and a second channel region; a gate dielectric layer formed on the first, second, and third surface regions of the first silicon fin region, and on the third and fourth surface regions of the second silicon fin region; a dual-gate FinFET, comprising the second drain, source and channel regions in the second silicon fin region; and a tri-gate FinFET, comprising the first drain, source and channel regions.

What is claimed is: 
     
         1 . An integrated circuit apparatus, the apparatus comprising:
 a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a silicon layer overlying an insulator layer;   a first silicon fin region formed in a first region of the silicon layer, the first silicon fin region comprising a first source region, a first drain region, and a first channel region, the first channel region having a first surface region, a second surface region, and a third surface region;   a second silicon fin region formed in a second region of the silicon layer, the second silicon fin region comprising a second source region, a second drain region, and a second channel region, the second channel region having a fourth surface region, a fifth surface region and a sixth surface region;   a gate dielectric layer formed on the first, second, and third surface regions of the first silicon fin region, and on the third and fourth surface regions of the second silicon fin region;   a dual-gate FinFET, comprising the second drain, source and channel regions in the second silicon fin region, the dual-gate FinFET having a first gate electrode and a second gate electrode, the first gate electrode overlying the gate dielectric on the third surface region of the second silicon fin region, the second gate electrode overlying the gate dielectric on the fourth surface region of the second silicon fin region; and   a tri-gate FinFET, comprising the first drain, source and channel regions in the first silicon fin region, the tri-gate FinFET further comprising a third gate electrode overlying the gate dielectric on the first, second, and third surface regions of the first silicon fin region.   
     
     
         2 . The apparatus of  claim 1 , wherein the dual-gate FinFET further comprising a silicon nitride layer overlying the sixth surface region in the second silicon fin region, the nitride layer being configured to electrically insulate the first gate electrode from the second gate electrode. 
     
     
         3 . The apparatus of  claim 1 , wherein the source and drain regions of the dual-gate FinFET are elevated. 
     
     
         4 . The apparatus of  claim 1 , wherein the source and drain regions of the tri-gate FinFET are elevated. 
     
     
         5 . The apparatus of  claim 1 , wherein the silicon layer comprises a thickness of about 5-100 nm. 
     
     
         6 . The apparatus of  claim 1 , wherein the channel region of the dual-gate FinFET comprises a width of about 5-50 nm and a length of about 5-30 nm. 
     
     
         7 . The apparatus of  claim 1 , wherein the channel region of the tri-gate FinFET comprises a width of about 5-50 nm and a length of about 5-30 nm. 
     
     
         8 . The apparatus of  claim 1 , wherein the dual-gate FinFET is operated in a weak inversion region.