Sram memory having subarrays with common io block

Abstract

A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block. The IO block further includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines

What is claimed is: 
     
         1 . A static random access memory device, comprising:
 an array comprising a plurality memory cells, wherein the array further comprises:
 a first sub array comprising:
 a first plurality of memory cells of the plurality of memory cells, and 
 a first plurality of bit lines connected to the first plurality of memory cells; and 
 
 a second sub array comprising:
 a second plurality of memory cells of the plurality of memory cells, and 
 a second plurality of bit lines connected to the second plurality of memory cells, wherein the second sub array is approximately identical to the first sub array; and 
 
   an input output (IO) block placed between the first sub array and the second sub array, wherein the first plurality of bit lines extend from the first sub array to the IO block, and wherein the second plurality of bit lines extend from the second sub array to the IO block.   
     
     
         2 . The static random memory device of  claim 1 , wherein the IO block comprises an output latch configured to receive data read from the first plurality of bit lines and the second plurality of bit lines. 
     
     
         3 . The static random access memory of  claim 1 , further comprising:
 a first read multiplexer coupled to receive data from the first plurality of bit lines, and configured provide a first output in response to a first column select signal; and   a second read multiplexer coupled to receive data from the second plurality of bit lines, and configured provide a second output in response to a second column select signal.   
     
     
         4 . The static random access memory of  claim 1 , further comprising:
 a first sense amplifier coupled to receive data from the first plurality of bit lines and provide a first output to an output latch; and   a second sense amplifier coupled to receive data from the second plurality of bit lines and provide a second output to an output latch.   
     
     
         5 . The static random access memory of  claim 4 , wherein the first sense amplifier is not coupled to receive data from the second plurality of bit lines, and wherein the second sense amplifier is not coupled to receive data from the first plurality of bit lines. 
     
     
         6 . The static random access memory of  claim 4 , wherein the first and second sense amplifiers are configured with tri-state logic. 
     
     
         7 . The static random access memory of  claim 1 , further comprising:
 a plurality of word lines connected to the first sub array and the second sub array; and   a row decoder connected to the plurality of word lines.   
     
     
         8 . The static random access memory of  claim 1 , further comprising a third sub array and a fourth sub array. 
     
     
         9 . The static random access memory of  claim 8 , wherein the first sub array and third sub array are positioned on a first side of the IO block and the second sub array and the fourth sub array are positioned on a second side of the IO block opposite the first side, and wherein the first sub array and the second sub array are positioned on a first side of a row decoder and the third sub array and the fourth sub array are positioned on a second side of the row decoder. 
     
     
         10 . The static random access memory of  claim 1 , further comprising a write controller coupled to the first plurality of bit lines and the second plurality of bit lines. 
     
     
         11 . A memory input/output (IO), comprising:
 an array comprising a plurality memory cells, wherein the array further comprises:
 a first sub array comprising:
 a first plurality of memory cells of the plurality of memory cells, and 
 a first plurality of bit lines connected to the first plurality of memory cells; and 
 
 a second sub array comprising:
 a second plurality of memory cells of the plurality of memory cells, and 
 a second plurality of bit lines connected to the second plurality of memory cells, wherein the second sub array is approximately identical to the first sub array; and 
 
   an input output (IO) block comprising a first side and a second side opposite the first side, wherein the first side is configured to receive the first plurality of bit lines extending from the first sub array to the IO block, and wherein the second side is configured to receive the second plurality of bit lines extending from the second sub array to the IO block.   
     
     
         12 . The memory IO of  claim 11 , wherein the IO block is placed between the first sub array and the second sub array. 
     
     
         13 . The memory IO of  claim 11 , further comprising a write controller coupled to the first plurality of bit lines and the second plurality of bit lines. 
     
     
         14 . The static random access memory of  claim 11 , further comprising a third sub array and a fourth sub array, wherein the first sub array and third sub array are positioned on a first side of the IO block and the second sub array and the fourth sub array are positioned on a second side of the IO block opposite the first side, and wherein the first sub array and the second sub array are positioned on a first side of a row decoder and the third sub array and the fourth sub array are positioned on a second side of the row decoder. 
     
     
         15 . The memory IO of  claim 11 , wherein the IO block comprises an output latch configured to receive data read from the first plurality of bit lines and the second plurality of bit lines. 
     
     
         16 . The memory IO of  claim 11 , further comprising:
 a first read multiplexer coupled to receive data from the first plurality of bit lines, and configured provide a first output in response to a first column select signal; and   a second read multiplexer coupled to receive data from the second plurality of bit lines, and configured provide a second output in response to a second column select signal.   
     
     
         17 . The memory IO of  claim 1 , further comprising:
 a first sense amplifier coupled to receive data from the first plurality of bit lines and provide a first output to an output latch; and   a second sense amplifier coupled to receive data from the second plurality of bit lines and provide a second output to the output latch.   
     
     
         18 . A method of forming a static random access memory device, the method comprising:
 forming an array comprising a plurality memory cells, wherein forming the array further comprises:
 forming a first sub array comprising:
 a first plurality of memory cells of the plurality of memory cells, and 
 a first plurality of bit lines connected to the first plurality of memory cells; and 
 
 forming a second sub array comprising:
 a second plurality of memory cells of the plurality of memory cells, and 
 a second plurality of bit lines connected to the second plurality of memory cells, wherein the second sub array is approximately identical to the first sub array; 
 
   forming an input output (IO) block placed between the first sub array and the second sub array;   extending the first plurality of bit lines from the first sub array to the IO block; and   extending the second plurality of bit lines from the second sub array to the IO block.   
     
     
         19 . The method of forming the static random access memory device of  claim 18 , further comprising writing data into the static random access memory device. 
     
     
         20 . The method of forming the static random access memory device of  claim 18 , further comprising reading data from the static random access memory device.