Memories for reading data corresponding to multiple addresses associated with a read command

Abstract

Memories might include an array of memory cells, a status register, and a controller for access of the array of memory cells. The controller might further be configured to perform a first read operation of a plurality of read operations in response to a read command associated with a plurality of addresses, store a first status value to the status register in response to data of the first read operation being available for readout, begin a second read operation of the plurality of read operations after completing the first read operation, and store a second value, different than the first value, to the status register in response to data of the second read operation being available for readout.

What is claimed is: 
     
         1 . A memory, comprising:
 an array of memory cells;   a status register; and   a controller for access of the array of memory cells, wherein the controller is configured to:
 perform a first read operation of a plurality of read operations on the array of memory cells in response to a read command associated with a plurality of addresses, each read operation of the plurality of read operations corresponding to a respective address of the plurality of addresses; 
 store a first status value to the status register in response to data of the first read operation being available for readout by an external device; 
 begin a second read operation of the plurality of read operations after completing the first read operation; and 
 store a second value, different than the first value, to the status register in response to data of the second read operation being available for readout by the external device. 
   
     
     
         2 . The memory of  claim 1 , wherein the controller is further configured to:
 for each read operation of the plurality of read operations:
 in response to data of that read operation being available for readout by the external device, store a respective value to the status register indicating to which address of the plurality of addresses the available data corresponds. 
   
     
     
         3 . The memory of  claim 1 , further comprising:
 an address queue comprising a plurality of address registers;   wherein the controller is further configured to store each address of the plurality of addresses to a respective address register of the plurality of address registers.   
     
     
         4 . The memory of  claim 3 , wherein the address queue further comprises a plurality of flag registers, each flag register of the plurality of flag registers corresponding to a respective address register of the plurality of address registers, and configured to indicate whether its respective address register contains a valid address. 
     
     
         5 . The memory of  claim 4 , wherein the controller is further configured to store a particular value to each flag register of the plurality of flag registers when storing an address of the plurality of addresses to its respective address register of the plurality of address registers. 
     
     
         6 . The memory of  claim 5 , wherein the controller is further configured to store a different value to each flag register of the plurality of flag registers in response to performing a read operation for the address stored in its respective address register of the plurality of address registers. 
     
     
         7 . The memory of  claim 1 , wherein the first status value and the second status value are each a status value of a plurality of status values, with each status value of the plurality of status values corresponding to a respective address of the plurality of addresses. 
     
     
         8 . The memory of  claim 7 , wherein each status value of the plurality of status values is different than each remaining status value of the plurality of status values, and wherein the controller is further configured to store an alternate status value to the status register, mutually exclusive of the plurality of status values, to indicate that no data of the plurality of read operations is available for readout by the external device. 
     
     
         9 . A memory, comprising:
 an array of memory cells;   a status register; and   a controller for access of the array of memory cells, wherein the controller is configured to:
 receive a read command associated with a plurality of addresses; 
 read data corresponding to a particular address of the plurality of addresses; 
 latch read data corresponding to the particular address for readout, and provide an indication that the read data corresponding to the particular address is available for readout; 
 begin reading data corresponding to a next address of the plurality of addresses after latching the read data corresponding to the particular address for readout; and 
 latch read data corresponding to the next address for readout, and provide an indication that the read data corresponding to the next address is available for readout; 
 wherein the indication that the read data corresponding to the particular address is available for readout is different than the indication that the read data corresponding to the next address is available for readout. 
   
     
     
         10 . The memory of  claim 9 , wherein the controller is further configured to:
 for each address of the plurality of addresses:
 begin reading data corresponding to that address after latching read data corresponding to an immediately prior address of the plurality of addresses for readout; and 
 latch read data corresponding to that address for readout, and provide an indication that the read data corresponding to that address is available for readout; 
 wherein a value of the indication that the read data corresponding to that address is available for readout is different than a value of the indication that the read data corresponding to any other address of the plurality of addresses is available for readout. 
   
     
     
         11 . The memory of  claim 9 , wherein the controller is further configured to provide an indication that no valid data is available for readout prior to providing the indication that the read data corresponding to the particular address is available for readout, wherein a value of the indication that no valid data is available for readout is different than a value of the indication that the read data corresponding to any address of the plurality of addresses is available for readout. 
     
     
         12 . The memory of  claim 9 , wherein the controller is further configured to read the data corresponding to the next address of the plurality of addresses without performing closing or startup overhead activities after reading the data corresponding to the particular address of the plurality of addresses. 
     
     
         13 . The memory of  claim 12 , wherein the controller is further configured to perform startup overhead activities in response to the read command before reading data corresponding to a first address of the plurality of addresses. 
     
     
         14 . The memory of  claim 12 , wherein the controller is further configured to perform the startup overhead activities in response to the read command only before reading the data corresponding to the first address of the plurality of addresses. 
     
     
         15 . The memory of  claim 13 , wherein the controller is further configured to perform closing overhead activities in response to the read command after reading data corresponding to a last address of the plurality of addresses. 
     
     
         16 . The memory of  claim 12 , wherein the controller is further configured to perform the closing overhead activities in response to the read command only after reading the data corresponding to the last address of the plurality of addresses. 
     
     
         17 . A memory, comprising:
 an array of memory cells;   a status register; and   a controller for access of the array of memory cells, wherein the controller is configured to:
 receive a read command associated with N addresses, wherein N is an integer value greater than one; 
 store the N addresses to a queue; 
 read data corresponding to a particular address of the queue; 
 latch the data corresponding to the particular address for readout, and provide an indication that the data corresponding to the particular address is available for readout; 
 read data corresponding to a next address of the queue after latching the data corresponding to the particular address for readout; and 
 latch the data corresponding to the next address for readout, and provide an indication that the data corresponding to the next address is available for readout; 
 wherein the indication that the data corresponding to the particular address is available for readout is different than the indication that the data corresponding to the next address is available for readout. 
   
     
     
         18 . The memory of  claim 17 , wherein the controller being configured to store the N addresses to the queue comprises the controller being configured to store the N addresses to a queue having a number of address registers greater than or equal to N. 
     
     
         19 . The memory of  claim 18 , wherein the controller is further configured to:
 store each address of the N addresses to a corresponding address register of the queue; and   for each address register of the queue receiving an address of the N addresses, store a particular value to a corresponding flag register of a plurality of flag registers.   
     
     
         20 . The memory of  claim 19 , wherein the controller being configured to read the data corresponding to the particular address of the queue further comprises the controller being configured to store a different value to the flag register of the plurality of flag registers corresponding to the address register of the plurality of address registers storing the particular address. 
     
     
         21 . The memory of  claim 19 , wherein the controller is further configured to store an additional address to a particular address register of the plurality of address registers after reading data corresponding to the address of the plurality of addresses stored in the particular address register. 
     
     
         22 . The memory of  claim 18 , wherein the controller is further configured to:
 store each address of the N addresses to a corresponding address register of the queue, wherein the queue comprises a number of address registers greater than N; and   store a particular value to an address register of the queue that does not store an address of the N addresses, wherein the particular value does not correspond to any valid storage location of the memory.