Data processing device and method

Abstract

A data processing device includes a first circuit and a second circuit. The first circuit includes a first front-end circuit configured to process first data to obtain first demodulated data, and a back-end circuit coupled to the first front-end circuit and configured to receive the first demodulated data. The second circuit includes a second front-end circuit configured to process second data to obtain second demodulated data, and a transmitter coupled to the second front-end circuit and configured to pack the second demodulated data into data packets and transmit the data packets of the second demodulated data to the first circuit. The back-end circuit is further configured to receive the second demodulated data, and process the first demodulated data and the second demodulated data.

What is claimed is: 
     
         1 . A data processing device comprising:
 a first circuit including:
 a first front-end circuit configured to process first data to obtain first demodulated data; and 
 a back-end circuit coupled to the first front-end circuit and configured to receive the first demodulated data; and 
   a second circuit including:
 a second front-end circuit configured to process second data to obtain second demodulated data; and 
 a transmitter coupled to the second front-end circuit and configured to:
 pack the second demodulated data into data packets; and 
 transmit the data packets of the second modulated data to the first circuit; 
 
   wherein the back-end circuit is further configured to:
 receive the second demodulated data, and 
 process the first demodulated data and the second demodulated data. 
   
     
     
         2 . The data processing device of  claim 1 , wherein the first circuit further includes a storage medium coupled to the back-end circuit and configured to store the second demodulated data. 
     
     
         3 . The data processing device of  claim 2 , wherein:
 the transmitter is further configured to transmit the second demodulated data to the storage medium, and   the back-end circuit is further configured to read the second demodulated data from the storage medium.   
     
     
         4 . The data processing device of  claim 1 , wherein the back-end circuit includes:
 a combiner coupled to the first front-end circuit and configured to combine the first demodulated data and the second demodulated data to generate combined data; and   a decoder coupled to the combiner and configured to decode the combined data.   
     
     
         5 . The data processing device of  claim 4 , wherein the combiner is further configured to synchronize the first demodulated data and the second demodulated data. 
     
     
         6 . The data processing device of  claim 5 , wherein the combiner is further configured to:
 obtain a synchronization marker from the second demodulated data, and   synchronize the first demodulated data and the second demodulated data based on the synchronization marker.   
     
     
         7 . The data processing device of  claim 1 , wherein the transmitter is further configured to add a synchronization marker to a packet head of one of the data packets. 
     
     
         8 . The data processing device of  claim 7 , wherein the data packets include Orthogonal Frequency Division Multiplexing (OFDM) symbols containing the second demodulated data. 
     
     
         9 . The data processing device of  claim 8 , wherein:
 the OFDM symbols are grouped into at least one data subframe, and   the synchronization marker includes at least one of a subframe number or an OFDM symbol label.   
     
     
         10 . The data processing device of  claim 1 , wherein the second circuit is further configured to:
 transmit the data packets to a storage medium of the first circuit, and   send a write-complete indication to the first circuit after transmitting one of the data packets to the storage medium.   
     
     
         11 . The data processing device of  claim 10 , wherein the first circuit is configured to send a read-complete indication to the second circuit after the back-end circuit reads the one of the data packets from the storage medium. 
     
     
         12 . The data processing device of  claim 10 , further comprising:
 a data link between the transmitter and the storage medium,   wherein the transmitter is configured to transmit the data packets through the data link,   
     
     
         13 . The data processing device of  claim 12 , further comprising:
 an instruction link between the first circuit and the second circuit, the instruction link being different from the data link,   wherein:
 the second circuit is configured to send the write-complete indication to the first circuit through the instruction link, and 
 the first circuit is configured to send the read-complete indication to the second circuit through the instruction link. 
   
     
     
         14 . The data processing device of  claim 1 , further comprising:
 one or more first antennas coupled to the first front-end circuit and configured to receive wireless signals, convert the received wireless signals to the first data, and send the first data to the first front-end circuit; and   one or more second antennas coupled to the second front-end circuit and configured to receive the wireless signals, convert the received wireless signals to the second data, and send the second data to the second front-end circuit.   
     
     
         15 . The data processing device of  claim 14 , wherein:
 the first front-end circuit includes:
 a first pre-circuit configured to pre-process the first data from the one or more first antenna to generate first pre-processed data; and 
 a first demodulator coupled to the first pre-circuit and configured to demodulate the first pre-processed data to generate the first demodulated data, and the second front-end circuit includes: 
 a second pre-circuit configured to pre-process the second data from the one or more second antennas to generate second pre-processed data; and 
 a second demodulator coupled to the second pre-circuit and configured to demodulate the second pre-processed data to generate the second demodulated data. 
   
     
     
         16 . The data processing device of  claim 15 , wherein:
 the first pre-circuit includes:
 a first signal circuit configured to perform at least one of filtering, adjustment, analog-to-digital (AD) conversion, or sampling on the first data; 
 a first fast Fourier transformer (FFT′er) coupled to the first signal circuit and configured to perform fast Fourier transform (FFT) on the first data processed by the first signal circuit; and 
 a first channel estimator coupled between the first FFT′er and the first demodulator, and configured to perform a first channel estimation to obtain a first channel value for demodulating the first data, and 
   the second pre-circuit includes:
 a second signal circuit configured to perform at least one of filtering, adjustment, analog-to-digital (AD) conversion, or sampling on the second data; 
 a second FFT′er coupled to the second signal circuit and configured to perform FFT on the second data processed by the second signal circuit; and 
 a second channel estimator coupled between the second FFT′er and the second demodulator, and configured to perform a second channel estimation to obtain a second channel value for demodulating the second data. 
   
     
     
         17 . The data processing device of  claim 1 , wherein the first circuit is integrated in a first chip and the second circuit is integrated in a second chip. 
     
     
         18 . The data processing device of  claim 1 ,
 wherein the transmitter is a first transmitter,   the data processing device further comprising:
 a third circuit including:
 a third front-end circuit configured to process third data to obtain third demodulated data; and 
 a second transmitter coupled to the third front-end circuit and configured to transmit the third demodulated data to the first circuit, 
 
 wherein the back-end circuit is further configured to process the first demodulated data, the second demodulated data, and the third demodulated data. 
   
     
     
         19 . A data processing method comprising:
 processing, by a first circuit, first data to obtain first demodulated data;   processing, by a second circuit, second data to obtain second demodulated data;   packing, by the second circuit, the second modulated data into data packets;   transmitting, by the second circuit, the data packets of the second modulated data to the first circuit; and   processing, by the first circuit, the first demodulated data and the second demodulated data.   
     
     
         20 . The data processing method of  claim 19 , wherein processing the first demodulated data and the second demodulated data includes:
 combining the first demodulated data and the second demodulated data to generate combined data; and   decoding the combined data.