Semiconductor device and method for fabricating the same

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, an intrinsically conductive pad positioned above the substrate, a stress relief structure positioned above the substrate and distant from the intrinsically conductive pad, and an external bonding structure positioned directly above the stress relief structure.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   an intrinsically conductive pad positioned above the substrate;   a stress relief structure positioned above the substrate and distant from the intrinsically conductive pad; and   an external bonding structure positioned directly above the stress relief structure.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the stress relief structure comprises a conductive frame and a plurality of insulating segments positioned within the conductive frame. 
     
     
         3 . The semiconductor device of  claim 2 , wherein each of the plurality of insulating segments has a square shape and the insulating segments are separated from each other. 
     
     
         4 . The semiconductor device of  claim 2 , further comprising a plurality of word lines positioned in the substrate and extending along a first direction, wherein each of the plurality of insulating segments has a rectangular shape and extends along a second direction perpendicular to the first direction. 
     
     
         5 . The semiconductor device of  claim 2 , further comprising a plurality of word lines positioned in the substrate and extending along a first direction, wherein each of the plurality of insulating segments has a rectangular shape and extends along a second direction diagonal with respect to the first direction. 
     
     
         6 . The semiconductor device of  claim 2 , further comprising a redistribution conductive layer positioned above the stress relief structure and the intrinsically conductive pad. 
     
     
         7 . The semiconductor device of  claim 6 , further comprising a stress-buffering layer positioned below the external bonding structure, wherein the stress-buffering layer is formed of a material having a coefficient of thermal expansion of less than about 20 ppm/° C. and a Young's Modulus of less than about 15 GPa. 
     
     
         8 . The semiconductor device of  claim 2 , wherein the external bonding structure comprises a bottom bonding layer positioned directly above the stress relief structure and a top bonding layer positioned above the bottom bonding layer. 
     
     
         9 . The semiconductor device of  claim 2 , wherein the external bonding structure comprises a bottom bonding layer positioned directly above the stress relief structure, a middle bonding layer positioned on the bottom bonding layer, and a top bonding layer positioned on the middle bonding layer. 
     
     
         10 . The semiconductor device of  claim 8 , wherein a width of the external bonding structure is less than a width of the stress relief structure. 
     
     
         11 . The semiconductor device of  claim 8 , further comprising a wiring layer positioned on the external bonding structure. 
     
     
         12 . The semiconductor device of  claim 11 , wherein a width of the wiring layer is less than a width of the external bonding structure. 
     
     
         13 . The semiconductor device of  claim 8 , further comprising two spacers positioned adjacent to two sides of the external bonding structure. 
     
     
         14 . A method for fabricating a semiconductor device, comprising:
 providing a substrate;   forming an intrinsically conductive pad above the substrate; and   forming a stress relief structure above the substrate and distant from the intrinsically conductive pad.   
     
     
         15 . The method for fabricating the semiconductor device of  claim 14 , wherein forming the stress relief structure above the substrate and distant from the intrinsically conductive pad comprises:
 forming a conductive frame above the substrate; and   forming a plurality of insulating segments within the conductive frame.   
     
     
         16 . The method for fabricating the semiconductor device of  claim 15 , further comprising:
 forming a redistribution conductive layer above the intrinsically conductive pad and the stress relief structure.   
     
     
         17 . The method for fabricating the semiconductor device of  claim 16 , further comprising:
 forming a plurality of passivation layers above the redistribution conductive layer and forming a first pad opening in the plurality of passivation layers.   
     
     
         18 . The method for fabricating the semiconductor device of  claim 17 , further comprising:
 performing a passivation process comprising soaking the first pad opening with a precursor, wherein the precursor is dimethylaminotrimethylsilane or tetramethylsilane.   
     
     
         19 . The method for fabricating the semiconductor device of  claim 17 , further comprising:
 performing a cleaning process, wherein the cleaning process comprises applying a remote plasma to the first pad opening.   
     
     
         20 . The method for fabricating the semiconductor device of  claim 18 , further comprising:
 forming an external bonding structure on the redistribution conductive layer;   wherein the external bonding structure comprises a bottom bonding layer formed on the redistribution conductive layer and a top bonding layer formed on the bottom bonding layer.