Vectored flip-flop

Abstract

An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

We claim: 
     
         1 . An apparatus comprising:
 a clock driver to provide at least two clocks; and   a chain of flip-flops coupled to the clock driver to receive the at least two clocks, wherein the chain of flip-flops comprises a first flip-flop and a second flip-flop, wherein a memory circuitry of the first flip-flop is coupled to a multiplexer, wherein the multiplexer is coupled to an input of the second flip-flop.   
     
     
         2 . The apparatus of  claim 1 , wherein the multiplexer is coupled to the memory circuitry of the first flip-flop on metal layer  1  (M 1 ) or a metal lower than M 1 . 
     
     
         3 . The apparatus of  claim 1 , wherein the chain of flip-flops comprises a third flip-flop coupled to the second flip-flop, wherein a memory circuitry of the second flipflop is coupled to a second multiplexer which is coupled to an input of the third flip-flop. 
     
     
         4 . The apparatus of  claim 3 , wherein the second multiplexer is coupled to the memory circuitry of the second flip-flop on metal layer  1  (M 1 ) or a metal lower than M 1 . 
     
     
         5 . The apparatus of  claim 1 , wherein the chain of flip-flops is part of a vectored flip-flop circuitry. 
     
     
         6 . The apparatus of  claim 1 , wherein the clock driver comprises:
 a first inverter to receive an input clock and to generate a first clock which is an inversion of the input clock; and   a second inverter coupled in series with the first inverter, wherein the second inverter is to generate a second clock which is an inversion of the first clock, wherein the first clock and the second clock are the at least two clocks.   
     
     
         7 . The apparatus of  claim 1  comprises a scan gadget coupled to an input of the first flip-flop, wherein the scan gadget is to selectively provide one of a data input or a scan input to the first flip-flop. 
     
     
         8 . An apparatus comprising:
 a clock driver to provide at least two clocks; and   a chain of flip-flops coupled to the clock driver to receive the at least two clocks, wherein the chain of flip-flops comprises a first flip-flop and a second flip-flop, wherein a memory circuitry of the first flip-flop is coupled to a pass-gate, wherein the pass-gate is controllable by a scan control, wherein the pass-gate is coupled to an input of the second flip-flop.   
     
     
         9 . The apparatus of  claim 8 , wherein the pass-gate is coupled to the memory circuitry of the first flip-flop on metal layer  1  (M 1 ) or a metal lower than M 1 . 
     
     
         10 . The apparatus of  claim 8 , wherein the chain of flip-flops comprises a third flip-flop coupled to the second flip-flop, wherein a memory circuitry of the second flipflop is coupled to a second pass-gate which is coupled to an input of the third flip-flop. 
     
     
         11 . The apparatus of  claim 10 , wherein the second pass-gate is controllable by the scan control. 
     
     
         12 . The apparatus of  claim 10 , wherein the second pass-gate is coupled to the memory circuitry of the second flip-flop on metal layer  1  (M 1 ) or a metal lower than M 1 . 
     
     
         13 . The apparatus of  claim 8 , wherein the chain of flip-flops is part of a vectored flip-flop circuitry. 
     
     
         14 . The apparatus of  claim 8 , wherein the clock driver comprises:
 a first inverter to receive an input clock and to generate a first clock which is an inversion of the input clock; and   a second inverter coupled in series with the first inverter, wherein the second inverter is to generate a second clock which is an inversion of the first clock, wherein the first clock and the second clock are the at least two clocks.   
     
     
         15 . A system comprising:
 a memory;   a processor coupled to the memory;   an antenna coupled to the processor, wherein the processor includes a vectored flip-flop circuitry which comprises:
 a clock driver to provide at least two clocks; and 
 a chain of flip-flops coupled to the clock driver to receive the at least two clocks, wherein the chain of flip-flops comprises a first flip-flop and a second flip-flop, wherein a memory circuitry of the first flip-flop is coupled to a selection circuitry, wherein the selection circuitry is coupled to an input of the second flip-flop. 
   
     
     
         16 . The system of  claim 15 , wherein the selection circuitry is coupled to the memory circuitry of the first flip-flop on metal layer  1  (M 1 ) or a metal lower than M 1 . 
     
     
         17 . The system of  claim 15 , wherein the chain of flip-flops comprises a third flip-flop coupled to the second flip-flop, wherein a memory circuitry of the second flipflop is coupled to a second selection circuitry which is coupled to an input of the third flip-flop. 
     
     
         18 . The system of  claim 17 , wherein the second selection circuitry is coupled to the memory circuitry of the second flip-flop on metal layer  1  (M 1 ) or a metal lower than M 1 . 
     
     
         19 . The system of  claim 15 , wherein the selection circuitry is one of a multiplexer or a pass-gate. 
     
     
         20 . The system of  claim 15 , wherein the clock driver comprises:
 a first inverter to receive an input clock and to generate a first clock which is an inversion of the input clock; and   a second inverter coupled in series with the first inverter, wherein the second inverter is to generate a second clock which is an inversion of the first clock, wherein the first clock and the second clock are the at least two clocks.