Fin-Like Field Effect Transistors Having High Mobility Strained Channels and Methods of Fabrication Thereof

Abstract

Fin-like field effect transistors (FinFETs) having high mobility strained channels and methods of fabrication thereof are disclosed herein. An exemplary method includes forming a first silicon fin in a first type FinFET device region and a second silicon fin in a second type FinFET device region. First epitaxial source/drain features and second epitaxial source/drain features are formed respectively over first source/drain regions of the first silicon fin second source/drain regions of the second silicon fin. A gate replacement process is performed to form a gate structure over a first channel region of the first silicon fin and a second channel region of the second silicon fin. During the gate replacement process, a masking layer covers the second channel region of the second silicon fin when a silicon germanium channel capping layer is formed over the first channel region of the first silicon fin.

What is claimed is: 
     
         1 . A device comprising:
 a first fin structure and a second fin structure disposed over a substrate, the first and second fin structures including a first sidewall surface and an opposing second sidewall surface and a top surface extending from the first sidewall surface to the second sidewall surface;   a capping layer that includes silicon and germanium disposed directly on the first sidewall surface, the second sidewall surface and the top surface of the first fin structure;   a first gate dielectric layer disposed directly on the first sidewall surface, the second sidewall surface and the top surface of the second fin structure; and   a first gate electrode disposed over the capping layer and a second gate electrode disposed over the first gate dielectric layer.   
     
     
         2 . The device of  claim 1 , wherein the first gate dielectric layer extends form the second fin structure to the first fin structure such that the first gate dielectric layer is disposed directly on the capping layer disposed directly on the first sidewall surface, the second sidewall surface and the top surface of the first fin structure. 
     
     
         3 . The device of  claim 1 , further comprising a second gate dielectric layer disposed on the capping layer disposed directly on the first sidewall surface, the second sidewall surface and the top surface of the first fin structure, the second gate dielectric layer disposed between the first gate electrode and the capping layer and formed of different material than the first gate dielectric layer. 
     
     
         4 . The device of  claim 1 , wherein the first gate electrode is formed of a different material than the second gate electrode, and
 wherein the first gate electrode interfaces with the second gate electrode.   
     
     
         5 . The device of  claim 1 , further comprising a source/drain feature disposed on the first fin structure, and
 wherein the capping layer includes a first concentration of germanium and the source/drain feature includes a second concentration of germanium that is different.   
     
     
         6 . The device of  claim 5 , wherein the second concentration of germanium is greater than the first concentration of germanium. 
     
     
         7 . The device of  claim 1 , wherein the first fin structure is associated with a first transistor having a first-type of conductivity and the second fin structure is associated with a second transistor having a second-type of conductivity, the second-type of conductivity being opposite the first-type of conductivity. 
     
     
         8 . The device of  claim 7 , wherein the first-type of conductivity is p-type and the second-type of conductivity of n-type. 
     
     
         9 . A device comprising:
 a first semiconductor fin structure disposed over a first-type device region of a substrate and a second semiconductor fin structure disposed over a second-type device region of the substrate, the second-type being opposite the first-type;   a capping layer that includes silicon and germanium disposed directly on a top surface and opposing sidewall surfaces of the first semiconductor fin structure;   a gate dielectric layer disposed directly on a top surface and opposing sidewall surfaces of the second semiconductor fin structure and extending to the capping layer disposed on the first semiconductor fin structure; and   a first gate electrode disposed over the capping layer and a second gate electrode disposed over the gate dielectric layer.   
     
     
         10 . The device of  claim 9 , wherein the gate dielectric layer extends along the opposing sidewalls and top surface of the first semiconductor fin structure, and
 wherein the capping layer is disposed between the opposing sidewalls and top surface of the first semiconductor fin structure and the gate dielectric layer extending along the opposing sidewalls and top surface of the first semiconductor fin structure such that the gate dielectric layer is prevented form interfacing with the first semiconductor fin structure by the capping layer.   
     
     
         11 . The device of  claim 9 , wherein the first gate electrode is formed of the same material as the second gate electrode. 
     
     
         12 . The device of  claim 9 , wherein the first gate electrode is formed of a different material than the second gate electrode, and
 wherein the first and second gate electrodes extend to the same height above the substrate.   
     
     
         13 . The device of  claim 9 , wherein the first-type is p-type and the second-type is n-type. 
     
     
         14 . The device of  claim 9 , further comprising a dielectric isolation feature disposed on the substrate between the first and second semiconductor fin structures, and
 wherein the capping layer interfaces with the dielectric isolation feature.   
     
     
         15 . The device of  claim 14 , wherein the dielectric isolation feature extends continuously from the first semiconductor fin structure to the second semiconductor fin structure, and
 wherein the gate dielectric layer interfaces with the dielectric isolation feature.   
     
     
         16 . An integrated circuit device comprising:
 a first silicon fin in a first type FinFET device region;   a second silicon fin in a second type FinFET device region;   a gate structure disposed over a first channel region of the first silicon fin and a second channel region of the second silicon fin, wherein the first channel region is disposed between first source/drain regions of the first silicon fin and the second channel region is disposed between second source/drain regions of the second silicon fin; and   a channel capping layer disposed between the gate structure and the first channel region of the first silicon fin, wherein the channel capping layer includes silicon and germanium.   
     
     
         17 . The integrated circuit device of  claim 16 , further comprising an isolation feature that surrounds a portion of the first silicon fin and a portion of the second silicon fin, thereby defining the first channel region of the first silicon fin and the second channel region of the second silicon fin, and wherein the channel capping layer is not disposed between the isolation feature and the portion of the first silicon fin. 
     
     
         18 . The integrated circuit device of  claim 16 , wherein the gate structure includes a first high-k dielectric layer and a first metal gate electrode disposed over the first channel region of the first silicon fin and a second high-k dielectric and a second metal gate electrode disposed over the second channel region of the second silicon fin. 
     
     
         19 . The integrated circuit device of  claim 16 , further comprising:
 first epitaxial source/drain features disposed over the first source/drain regions of the first silicon fin, wherein the first epitaxial source/drain features includes silicon and germanium;   second epitaxial source/drain features disposed over the second source/drain regions of the second silicon fin, wherein the second epitaxial source/drain features include silicon; and   wherein a concentration of the germanium of the first epitaxial source/drain features is greater than a concentration of the germanium of the channel capping layer.   
     
     
         20 . The integrated circuit device of  claim 19 , wherein the concentration of the germanium of the first epitaxial source/drain features is about 30% to about 75% and the concentration of the germanium of the channel capping layer is about 10% to about 30%.