Three-Dimensional Memory Devices and Fabricating Methods Thereof

Abstract

Embodiments of 3D memory devices and fabricating methods are disclosed. The disclosed 3D memory device comprises: an alternating conductor/dielectric stack on a substrate; a channel hole penetrating the alternating dielectric stack; an epitaxial layer on a bottom of the channel hole and in contact with the substrate; a functional layer covering a sidewall of the channel hole; and a channel structure covering the functional layer, and being in electrical contact with the epitaxial layer through a top surface of the epitaxial layer as well as a sidewall and a bottom surface of a recess in the epitaxial layer.

What is claimed is: 
     
         1 . A three-dimensional (3D) memory device, comprising:
 an alternating conductor/dielectric stack on a substrate;   a channel hole penetrating the alternating dielectric stack;   an epitaxial layer on a bottom of the channel hole and in contact with the substrate;   a functional layer covering a sidewall of the channel hole; and   a channel structure covering the functional layer, and being in electrical contact with the epitaxial layer through a top surface of the epitaxial layer as well as a sidewall and a bottom surface of a recess in the epitaxial layer.   
     
     
         2 . The device of  claim 1 , wherein the channel structure is in contact with the functional layer at the top surface of the epitaxial layer. 
     
     
         3 . The device of  claim 1 , wherein the functional layer is in contact with the epitaxial layer. 
     
     
         4 . The device of  claim 1 , wherein the functional layer comprises a barrier layer on the sidewall of the channel hole. 
     
     
         5 . The device of  claim 4 , wherein the barrier layer is in contact with the conductor/dielectric stack and the epitaxial layer. 
     
     
         6 . The device of  claim 5 , wherein the barrier layer consists of a silicon oxide layer or a combination of silicon oxide/silicon nitride/silicon oxide layers. 
     
     
         7 . The device of  claim 5 , wherein the barrier layer comprises high-k dielectrics. 
     
     
         8 . The device of  claim 5 , wherein the barrier layer comprises aluminum oxide. 
     
     
         9 . The device of  claim 4 , wherein a thickness of the barrier layer is in a range from about 4 nm to about 15 nm. 
     
     
         10 . The device of  claim 4 , wherein the functional layer further comprises: a storage layer on a surface of the barrier layer and a tunneling layer on a surface of the storage layer. 
     
     
         11 . The device of  claim 10 , wherein the barrier layer is configured to block an outflow of electronic charges; the storage layer is configured to store electronic charges during operation of the 3D memory device; the tunneling layer is configured to tunnel electronic charges. 
     
     
         12 . The device of  claim 10 , wherein a thickness of the tunneling layer is in a range from about 5 nm to about 15 nm. 
     
     
         13 . The device of  claim 10 , wherein the channel structure is in contact with the tunneling layer. 
     
     
         14 . The device of  claim 1 , wherein the alternating conductor/dielectric stack comprises a plurality of conductor/dielectric layer pairs stacked in a vertical direction, wherein each conductor/dielectric layer pair includes a conductor layer and a dielectric layer. 
     
     
         15 . The device of  claim 14 , wherein a material of the conductive layer consists of W Co, Cu, Al, polysilicon, silicides, or a combination thereof. 
     
     
         16 . The device of  claim 14 , wherein a material of the dielectric layer consists of silicon oxide. 
     
     
         17 . The device of  claim 1 , wherein the channel structure is a semiconductor layer. 
     
     
         18 . The device of  claim 1 , wherein the channel structure comprises: a first channel layer covering the functional layer; and a second channel layer covering the first channel structure and being in electric contact with the epitaxial layer. 
     
     
         19 . The device of  claim 18 , wherein a material of the first channel layer includes amorphous silicon, polycrystalline silicon or monocrystalline silicon. 
     
     
         20 . The device of  claim 18 , wherein a material of the second channel layer is different from a material of the first channel layer.