Semiconductor packages

Abstract

A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a package substrate including a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer;   a semiconductor chip disposed on the package substrate to include a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column;   first bonding wires connecting the first column of chip pads to the first column of bond fingers, respectively; and   second bond fingers connecting the second column of chip pads to the second column of bond fingers, respectively,   wherein the first column of chip pads includes a first signal pad, a ground pad, and a second signal pad which are sequentially arrayed in the first column,   wherein the second column of chip pads includes a first power pad, a third signal pad, and a second power pad which are sequentially arrayed in the second column, and   wherein the third signal pad and the ground pad are arrayed side-by-side in a row.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the third signal pad is closer to the ground pad than the first and second signal pads. 
     
     
         3 . The semiconductor package of  claim 1 , wherein the first signal pad, the third signal pad, and the second signal pad are arrayed in a zigzag fashion along a direction which is parallel with the first and second columns. 
     
     
         4 . The semiconductor package of  claim 1 ,
 wherein the first column of chip pads are located between an edge of the semiconductor chip and the second column of chip pads; and   wherein the first column of bond fingers are located between the edge of the semiconductor chip and the second column of bond fingers.   
     
     
         5 . The semiconductor package of  claim 4 , wherein the first bonding wires are shorter than the second bonding wires. 
     
     
         6 . The semiconductor package of  claim 1 ,
 wherein the first column of bond fingers includes a first signal bond finger, a ground bond finger, and a second signal bond finger which are sequentially arrayed;   wherein the second column of bond fingers includes a first power bond finger, a third signal bond finger, and a second power bond finger which are sequentially arrayed; and   wherein the third signal bond finger and the ground bond finger are arrayed side-by-side in a row.   
     
     
         7 . The semiconductor package of  claim 6 , wherein the third signal bond finger is closer to the ground bond finger than the first and second signal bond fingers. 
     
     
         8 . The semiconductor package of  claim 6 , further comprising:
 a third signal trace extending from the third signal bond finger;   a first power trace extending from the first power bond finger;   a second power trace extending from the second power bond finger; and   a ground trace extending from the ground bond finger and partially overlapping with the third signal trace in a vertical direction,   wherein the third signal trace is located between the first and second power traces in the second layer to be electromagnetically shielded by the first and second power traces, and   wherein the third signal trace is electromagnetically shielded by the ground trace in the vertical direction.   
     
     
         9 . The semiconductor package of  claim 1 , further comprising:
 a first layer of traces extending from respective ones of the first column of bond fingers; and   a second layer of traces extending from respective ones of the second column of bond fingers,   wherein the first layer of traces are located to vertically overlap with the second layer of traces, respectively.   
     
     
         10 . The semiconductor package of  claim 1 ,
 wherein the semiconductor chip is stacked on a top surface of the package substrate;   wherein the first layer is located between the second layer and the top surface of the package substrate; and   wherein the first column of bond fingers and the second column of bond fingers are located at different levels.   
     
     
         11 . A semiconductor package comprising:
 a package substrate including a first column of bond fingers arrayed in a first layer and a second column of bond fingers arrayed in a second layer;   a first semiconductor chip disposed on the package substrate to include a first column of chip pads arrayed in a first column, a second column of chip pads arrayed in a second column, a third column of chip pads arrayed in a third column located at one side of the second column opposite to the first column, and common interconnection lines for connecting the third column of chip pads to the first column of chip pads;   a second semiconductor chip disposed on the first semiconductor chip to include a first column of chip pads and a second column of chip pads;   first bonding wires connecting the first column of bond fingers to the first column of chip pads of the first semiconductor chip;   second bonding wires connecting the second column of bond fingers to the second column of chip pads of the first semiconductor chip;   third bonding wires connecting the first column of chip pads of the second semiconductor chip to the third column of chip pads of the first semiconductor chip; and   fourth bonding wires connecting the second column of chip pads of the second semiconductor chip to the second column of chip pads of the first semiconductor chip.   
     
     
         12 . The semiconductor package of  claim 11 ,
 wherein the first column of chip pads of the first semiconductor chip includes a first signal pad, a ground pad, and a second signal pad which are sequentially arrayed;   wherein the second column of chip pads of the first semiconductor chip includes a first power pad, a third signal pad, and a second power pad which are sequentially arrayed; and   wherein the third signal pad of the first semiconductor chip and the ground pad of the first semiconductor chip are arrayed side-by-side in a row.   
     
     
         13 . The semiconductor package of  claim 12 , wherein the third signal pad of the first semiconductor chip is closer to the ground pad of the first semiconductor chip than the first and second signal pads of the first semiconductor chip. 
     
     
         14 . The semiconductor package of  claim 12 ,
 wherein the first column of chip pads of the second semiconductor chip includes a first signal pad, a ground pad, and a second signal pad which are sequentially arrayed in the same order as the first signal pad, the ground pad, and the second signal pad of the first semiconductor chip are arrayed;   wherein the second column of chip pads of the second semiconductor chip includes a first power pad, a third signal pad, and a second power pad which are sequentially arrayed in the same order as the first power pad, the third signal pad, and the second power pad of the first semiconductor chip are arrayed; and   wherein the third signal pad and the ground pad of the second semiconductor chip are arrayed side-by-side in a row.   
     
     
         15 . The semiconductor package of  claim 12 , wherein the first signal pad, the third signal pad, and the second signal pad of the first semiconductor chip are arrayed in a zigzag fashion. 
     
     
         16 . The semiconductor package of  claim 11 ,
 wherein the third column of chip pads of the first semiconductor chip includes a first extension signal pad, an extension ground pad, and a second extension signal pad which are sequentially arrayed; and   wherein the first extension signal pad, the extension ground pad, and the second extension signal pad of the first semiconductor chip are electrically connected to the first signal pad, the ground pad, and the second signal pad of the first semiconductor chip through the common interconnection lines of the first semiconductor chip, respectively.   
     
     
         17 . The semiconductor package of  claim 11 , wherein the common interconnection lines of the first semiconductor chip are conductive lines that extend from the third column of chip pads of the first semiconductor chip, detour the second column of chip pads of the first semiconductor chip, and reach the first column of chip pads of the first semiconductor chip. 
     
     
         18 . The semiconductor package of  claim 11 , wherein the second semiconductor chip further includes:
 a third column of chip pads located at one side of the second column of chip pads of the second semiconductor chip opposite to the first column of chip pads of the second semiconductor chip; and   common interconnection lines connecting the third column of chip pads of the second semiconductor chip to respective ones of the first column of chip pads of the second semiconductor chip.   
     
     
         19 . The semiconductor package of  claim 11 ,
 wherein the first column of bond fingers includes a first signal bond finger, a ground bond finger, and a second signal bond finger which are sequentially arrayed;   wherein the second column of bond fingers includes a first power bond finger, a third signal bond finger, and a second power bond finger which are sequentially arrayed; and   wherein the third signal bond finger and the ground bond finger are arrayed side-by-side in a row.   
     
     
         20 . The semiconductor package of  claim 19 , further comprising:
 a third signal trace extending from the third signal bond finger;   a first power trace extending from the first power bond finger;   a second power trace extending from the second power bond finger; and   a ground trace extending from the ground bond finger and partially overlapping with the third signal trace in a vertical direction,   wherein the third signal trace is located between the first and second power traces in the second layer to be electromagnetically shielded by the first and second power traces, and   wherein the third signal trace is electromagnetically shielded by the ground trace in the vertical direction.