Integrated circuit layout diagram system

Abstract

An IC layout diagram generation system includes a processor and a storage medium including computer program code configured to place a cell in an IC layout diagram, route a second metal segment to the cell by positioning the second metal segment along a first plurality of tracks having a first pitch in a first direction, route a third metal segment to the second metal segment by positioning the third metal segment along a second plurality of tracks having a second pitch in a second direction perpendicular to the first direction, and route a fourth metal segment to the third metal segment by positioning the fourth metal segment along a third plurality of tracks having a third pitch in the first direction, the third pitch being smaller than the second pitch. An IC layout file is generated based on the cell and the second, third, and fourth metal segments.

What is claimed is: 
     
         1 . An integrated circuit (IC) layout diagram generation system comprising:
 a processor; and   a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the system to:
 place a cell comprising a first metal segment in an IC layout diagram; 
 route a second metal segment to the cell by positioning the second metal segment along a first plurality of tracks having a first pitch in a first direction; 
 route a third metal segment to the second metal segment by positioning the third metal segment along a second plurality of tracks having a second pitch in a second direction perpendicular to the first direction; 
 route a fourth metal segment to the third metal segment by positioning the fourth metal segment along a third plurality of tracks having a third pitch in the first direction; and 
 generate an IC layout file based on the cell, the second metal segment, the third metal segment, and the fourth metal segment, 
 wherein the third pitch is smaller than the second pitch. 
   
     
     
         2 . The IC layout diagram generation system of  claim 1 , wherein
 the cell has a cell height in the first direction, and   a ratio of the cell height to the first pitch is equal to or less than five.   
     
     
         3 . The IC layout diagram generation system of  claim 1 , wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to:
 route a fifth metal segment to the fourth four segment by positioning the fifth metal segment along a fourth plurality of tracks having a fourth pitch in the second direction, wherein the fourth pitch is larger than the second pitch and the third pitch.   
     
     
         4 . The IC layout diagram generation system of  claim 3 , wherein at least one of
 a ratio of the second pitch to the third pitch is greater than or equal to 1.25, or   a ratio of the fourth pitch to the third pitch is greater than or equal to 1.3.   
     
     
         5 . The IC layout diagram generation system of  claim 1 , wherein
 the cell is one cell of a plurality of cells, and   the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to place the plurality of cells in the IC layout diagram based on routing of each of a plurality of second metal segments comprising the second metal segment, a plurality of third metal segments comprising the third metal segment, and a plurality of fourth metal segments comprising the fourth metal segment.   
     
     
         6 . The IC layout diagram generation system of  claim 1 , wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to:
 perform a design rule check on the fourth metal segment.   
     
     
         7 . The IC layout diagram generation system of  claim 1 , wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to generate a set of masks based on the IC layout diagram. 
     
     
         8 . An integrated circuit (IC) layout diagram generation system comprising:
 a processor; and   a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the system to:
 place a cell in an IC layout diagram, the cell having a cell height and comprising a first metal segment; 
 overlap the cell by positioning a second metal segment along a first plurality of tracks having a first pitch aligned with the cell height; 
 overlap the second metal segment by positioning a third metal segment along a second plurality of tracks having a second pitch perpendicular to the cell height; 
 overlap the third metal segment by positioning a fourth metal segment along a third plurality of tracks having a third pitch aligned with the cell height and smaller than the second pitch; and 
 generate an IC layout file based on the cell, the second metal segment, the third metal segment, and the fourth metal segment. 
   
     
     
         9 . The IC layout diagram generation system of  claim 8 , wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the system to overlap the first cell by overlapping the first metal segment of the cell with the second metal segment. 
     
     
         10 . The IC layout diagram generation system of  claim 8 , wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the system to overlap both of the third and fourth metal segments with a slot via. 
     
     
         11 . The IC layout diagram generation system of  claim 8 , wherein the first plurality of tracks comprises a total of five tracks positioned within the cell height. 
     
     
         12 . The IC layout diagram generation system of  claim 8 , wherein
 the second metal segment is a first second metal segment positioned along a first track of the first plurality of tracks, and   the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the system to:
 further overlap the cell by positioning a second second metal segment along a second track of the first plurality of tracks, wherein the first and second second metal segments are aligned coextensively in a direction of the cell height. 
   
     
     
         13 . The IC layout diagram generation system of  claim 12 , wherein
 the third metal segment is a first third metal segment positioned along a first track of the second plurality of tracks, and   the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the system to:
 overlap the second second metal segment by positioning a second third metal segment along the first track of the second plurality of tracks. 
   
     
     
         14 . An integrated circuit (IC) layout diagram generation system comprising:
 a processor; and   a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the system to:
 place first and second cells in an IC layout diagram, each of the first and second cells comprising a first metal segment; 
 execute at least a portion of an automated placement and routing (APR) algorithm whereby a first electrical connection to the first metal segment of the first cell and a second electrical connection to the first metal segment of the second cell are defined; and 
 generate an IC layout file based on the first cell, the second cell, the first electrical connection, and the second electrical connection, 
 wherein 
 each of the first and second electrical connections comprises a second metal segment aligned along a track of a first plurality of tracks having a first pitch in a first direction, a third metal segment aligned along a track of a second plurality of tracks having a second pitch in a second direction perpendicular to the first direction, and a fourth metal segment aligned along a track of a third plurality of tracks having a third pitch in the first direction, and 
 the third pitch is smaller than the second pitch. 
   
     
     
         15 . The IC layout diagram generation system of  claim 14 , wherein
 each of the first and second cells has a cell height in the first direction, and   a ratio of the cell height to the first pitch is equal to or less than five.   
     
     
         16 . The IC layout generation system of  claim 14 , wherein the APR algorithm comprises placing the second cell in the IC layout diagram after defining the first electrical connection. 
     
     
         17 . The IC layout generation system of  claim 14 , wherein the APR algorithm comprises defining each of the first and second electrical connections after placing each of the first and second cells in the IC layout diagram. 
     
     
         18 . The IC layout generation system of  claim 14 , wherein
 the first and second cells are a subset of a plurality of cells,   each cell of the plurality of cells comprises a corresponding first metal segment,   the APR algorithm comprises defining a plurality of electrical connections to corresponding first metal segments of the plurality of cells, and   each electrical connection of the plurality of electrical connections comprises a corresponding second metal segment aligned along a track of the first plurality of tracks, a corresponding third metal segment aligned along a track of the second plurality of tracks, and a corresponding fourth metal segment aligned along a track of the third plurality of tracks.   
     
     
         19 . The IC layout generation system of  claim 14 , wherein
 each of the first and second electrical connections comprises a fifth metal segment aligned along a track of a fifth plurality of tracks having a fourth pitch in the second direction,   a ratio of the second pitch to the third pitch is greater than or equal to 1.25, and   a ratio of the fourth pitch to the third pitch is greater than or equal to 1.3.   
     
     
         20 . The IC layout generation system of  claim 19 , wherein
 each of the first and second electrical connections comprises a slot via between the third and fourth metal segments and/or a slot via between the fourth and fifth metal segments.