Methods to tolerate programming and retention errors of crossbar memory arrays

Abstract

Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a plurality of access transistors configured to connect to a plurality of memory cells;   a local word line gating circuit configured to determine a first voltage based on a state of a storage element within the local word line gating circuit and set a local word line connected to each gate of the plurality of access transistors to the first voltage during a multiplication operation, the first voltage sets at least one transistor of the plurality of access transistors into a non-conducting state during the multiplication operation; and   a current summation circuit configured to be in communication with the plurality of access transistors, the current summation circuit is configured to aggregate memory cell currents from the plurality of memory cells during the multiplication operation while the local word line is set to the first voltage.   
     
     
         2 . The apparatus of  claim 1 , wherein:
 the current summation circuit is arranged on a first die; and   the plurality of memory cells is arranged on a second die.   
     
     
         3 . The apparatus of  claim 1 , wherein:
 the current summation circuit is configured to multiply a first current from a first memory cell of the plurality of memory cells by two times and multiply a second current from a second memory cell of the plurality of memory cells by four times prior to aggregating the memory cell currents.   
     
     
         4 . The apparatus of  claim 1 , wherein:
 the local word line gating circuit is configured to determine the first voltage based on a voltage applied to a global word line.   
     
     
         5 . The apparatus of  claim 1 , further comprising:
 a second plurality of access transistors configured to connect to a second plurality of memory cells;   a second local word line gating circuit configured to set a second local word line connected to gates of the second plurality of access transistors to a second voltage different from the first voltage during the multiplication operation; and   a second current summation circuit configured to aggregate memory cell currents from the second plurality of memory cells during the multiplication operation while the second local word line is set to the second voltage.   
     
     
         6 . The apparatus of  claim 5 , further comprising:
 a bit line connected to the plurality of memory cells and the second plurality of memory cells.   
     
     
         7 . The apparatus of  claim 1 , wherein:
 the first voltage sets each transistor of the plurality of access transistors into a non-conducting state during the multiplication operation.   
     
     
         8 . The apparatus of  claim 1 , further comprising:
 one or more control circuits configured to detect an electrical short within the plurality of memory cells and set the state of the storage element within the local word line gating circuit to a disabling state in response to detection of the electrical short.   
     
     
         9 . The apparatus of  claim 1 , wherein:
 the plurality of memory cells comprises non-volatile memory cells.   
     
     
         10 . The apparatus of  claim 1 , wherein:
 the storage element of the local word line gating circuit comprises a non-volatile storage element.   
     
     
         11 . A method, comprising:
 detecting an electrical short through a plurality of memory cells;   identifying a local word line gating circuit that controls a local word line connected to access transistors in series with the plurality of memory cells in response to detecting the electrical short;   determining a first voltage for the local word line during a multiplication operation;   configuring the local word line gating circuit such that the local word line is set to the first voltage during the multiplication operation;   performing the multiplication operation while the local word line is set to the first voltage, the multiplication operation includes aggregating currents flowing through the plurality of memory cells; and   storing a data value based on the aggregation of the currents flowing through the plurality of memory cells.   
     
     
         12 . The method of  claim 11 , wherein:
 the aggregating currents flowing through the plurality of memory cells includes multiplying a first current from a first memory cell of the plurality of memory cells by two times and multiplying a second current from a second memory cell of the plurality of memory cells by four times prior to aggregating the currents.   
     
     
         13 . The method of  claim 11 , wherein:
 the first voltage sets each of the access transistors into a non-conducting state during the multiplication operation.   
     
     
         14 . The method of  claim 11 , further comprising:
 configuring a second local word line gating circuit such that a second local word line connected to gates of a second plurality of access transistors in series with a second plurality of memory cells is set to a second voltage different from the first voltage during the multiplication operation, the second voltage sets each of the second plurality of access transistors into a conducting state during the multiplication operation.   
     
     
         15 . The method of  claim 11 , wherein:
 the local word line gating circuit includes a non-volatile storage element.   
     
     
         16 . The method of  claim 11 , wherein:
 the plurality of memory cells comprises non-volatile memory cells.   
     
     
         17 . An apparatus, comprising:
 a first plurality of access transistors configured to connect to a first plurality of memory cells;   a second plurality of access transistors configured to connect to a second plurality of memory cells;   a local word line gating circuit configured to set a local word line connected to the first plurality of access transistors to a first voltage during a multiplication operation, the first voltage sets at least one transistor of the first plurality of access transistors into a non-conducting state during the multiplication operation;   a current summation circuit configured to aggregate memory cell currents from the first plurality of memory cells during the multiplication operation while the local word line is set to the first voltage;   a second local word line gating circuit configured to set a second local word line connected to gates of the second plurality of access transistors to a second voltage different from the first voltage during the multiplication operation; and   a second current summation circuit configured to aggregate memory cell currents from the second plurality of memory cells during the multiplication operation while the second local word line is set to the second voltage.   
     
     
         18 . The apparatus of  claim 17 , wherein:
 the current summation circuit is configured to multiply a first current from a first memory cell of the first plurality of memory cells by two times prior to aggregating the memory cell currents from the first plurality of memory cells during the multiplication operation.   
     
     
         19 . The apparatus of  claim 17 , wherein:
 the first voltage sets each transistor of the first plurality of access transistors into a non-conducting state during the multiplication operation; and   the second voltage sets each transistor of the second plurality of access transistors into a conducting state during the multiplication operation.   
     
     
         20 . The apparatus of  claim 17 , wherein:
 the local word line gating circuit includes a non-volatile storage element and an analog multiplexor controlled by the non-volatile storage element; and   the first plurality of memory cells comprises non-volatile memory cells.