Apparatus and Method for Fast-Path Memory Operations

Abstract

Embodiments of the present invention provide tightly coupled off-die memory along with an interface bus and smart buffer logic so as to efficiently perform certain frequent or repetitive operations off of a core logic. Embodiments of the present invention relieve the core logic from performing certain repetitive or frequent memory accesses and other operations so as to allow such core logic to perform other more general or varied operations. In this way, the universal interface bus, smart buffer logic, and off-die memory are specially configured to perform certain select frequent and repetitive operations while the core logic may configured to perform other operations so as to provide an improved configuration with increased computational capability and reduced power budget.

1 - 32 . (canceled) 
     
     
         33 . A circuit, comprising:
 a logic core in an integrated circuit;   a memory control circuit configured to control a flow of memory information between the logic core and a memory that is external to the integrated circuit; and   buffer logic configured to couple the memory to the logic core, wherein the buffer logic is further configured to execute operations that comprise at least one of packet processing, traffic management, deep packet inspection, expedited head and tail pointer management, video processing and analytics, error detection, error correction, or pattern matching, wherein the buffer logic resides separately from and external to the logic core.   
     
     
         34 . The circuit of  claim 33  further comprising:
 an interface bus configured to manage traffic between the memory and the logic core. 
 
     
     
         35 . The circuit of  claim 34 , wherein the interface bus includes a driver circuit and a receiver circuit. 
     
     
         36 . The circuit of  claim 33 , wherein the operations are exclusively executed in the buffer logic. 
     
     
         37 . The circuit of  claim 33 , wherein the memory exclusively stores information for the operations. 
     
     
         38 . The circuit of  claim 37 , wherein an on-die memory in the integrated circuit stores results of the operations. 
     
     
         39 . The circuit of  claim 33  further comprising:
 an interposer that couples the logic core to the memory using a plurality of through-silicon vias. 
 
     
     
         40 . The circuit of  claim 33 , wherein the circuit is implemented in a 2.5-dimensional package. 
     
     
         41 . The circuit of  claim 33 , wherein the circuit is implemented in a three-dimensional package. 
     
     
         42 . The circuit of  claim 33 , wherein through-silicon vias couple the logic core to the memory. 
     
     
         43 . The circuit of  claim 33 , wherein microbumps couple the logic core to the memory. 
     
     
         44 . The circuit of  claim 33 , wherein the operations are performed on the integrated circuit only by the buffer logic. 
     
     
         45 . The circuit of  claim 33 , wherein performance of the operations is exclusively designated on the integrated circuit to the buffer logic. 
     
     
         46 . A method for handling operations, comprising:
 receiving information from a logic core implemented on an integrated circuit;   receiving information from an off-die memory external to the integrated circuit;   executing the operations using the information received from at least one of the off-die memory or the logic core, wherein the operations comprise at least one of traffic management, expedited head and tail pointer management, error detection, error correction, pattern matching, packet processing, image processing, or deep packet inspection, wherein the operations are executed on buffer logic residing separately from and external to the logic core; and   transmitting a first set of results of the operations to the off-die memory.   
     
     
         47 . The method of  claim 46 , further comprising transmitting a second set of results of the operations to the logic core. 
     
     
         48 . The method of  claim 46 , further comprising transmitting a second set of results of the operations to an on-die memory on the integrated circuit. 
     
     
         49 . The method of  claim 46 , further comprising managing traffic between the off-die memory and the logic core. 
     
     
         50 . The method of  claim 46 , further comprising providing an interposer configured to couple the logic core to the off-die memory. 
     
     
         51 . A data processing system, comprising:
 circuitry comprising:
 a logic core in an integrated circuit; 
 an interface bus that receives memory traffic from an off-die memory and the logic core; and 
 buffer logic, coupled to the interface bus and the off-die memory, wherein the buffer logic is configurable to execute operations that comprise at least one of packet processing, traffic management, deep packet inspection, expedited head and tail pointer management, error detection, error correction, pattern matching, or image processing, wherein the buffer logic resides external to the logic core; and 
   a processor, wherein the circuitry operates in cooperation with the processor.   
     
     
         52 . The data processing system of  claim 51 , wherein the buffer logic resides in the off-die memory. 
     
     
         53 . The data processing system of  claim 51 , wherein the interface bus includes a driver circuit and a receiver circuit. 
     
     
         54 . The data processing system of  claim 51 , wherein the operations are exclusively executed in the buffer logic. 
     
     
         55 . The data processing system of  claim 51 , wherein the off-die memory exclusively stores information for the operations. 
     
     
         56 . The data processing system of  claim 51 , wherein an on-die memory in the integrated circuit stores results of the operations. 
     
     
         57 . The data processing system of  claim 51 , wherein the circuitry further comprises:
 a memory control circuit configured to control a flow of memory information between the logic core and the off-die memory.   
     
     
         58 . The data processing system of  claim 51 , wherein the circuitry is implemented in a 2.5-dimensional package. 
     
     
         59 . The data processing system of  claim 51 , wherein the circuitry is implemented in a three-dimensional package. 
     
     
         60 . The data processing system of  claim 51  further comprising:
 an interposer that couples the logic core to the off-die memory using a plurality of through-silicon vias.