Multi-access memory system and a method to manufacture the system

Abstract

A multiple memory access system is disclosed. The system includes a first die disposed on a package substrate. A second die is stacked above the first die. The first die, the second die and the package substrate form a first package. An IC is placed within a close proximity of the first package where the first die communicates with the second die at a first data rate while the first die communicates with the IC at a second data rate. The first data rate is higher than the second data rate. Methods of forming a multi-access memory system are also disclosed.

What is claimed is: 
     
         1 . A method of forming a multiple-access memory system, the method comprising:
 forming first and second pads on a surface of a first die;   forming routings embedded below the surface of the first die, wherein each of the routings connects one of the first pads to one of the second pads; and   stacking a second die on the first die with interconnections that each couple the second die to the first die by physically contacting the second die and one of the second pads, wherein the first die and the second die are in a package, and wherein the first die is coupled to the second die via the first pads, the routings, the second pads, and the interconnections.   
     
     
         2 . The method of  claim 1  further comprising:
 placing an integrated circuit in the multiple-access memory system. 
 
     
     
         3 . The method of  claim 2 , wherein the second die and the integrated circuit are memory chips, and wherein the package and the integrated circuit are disposed on a surface of a printed circuit board. 
     
     
         4 . The method of  claim 3 , wherein a memory size of the second die is equivalent to a memory size of the integrated circuit. 
     
     
         5 . The method of  claim 3 , wherein the memory size of the second die is larger than a memory size of the integrated circuit. 
     
     
         6 . The method of  claim 1 , wherein the first die is one of a programmable logic device or a microprocessor. 
     
     
         7 . The method of  claim 2 , wherein the first die is operable to communicate with the second die at a first data rate, the first die is operable to communicate with the integrated circuit at a second data rate, and the first data rate is greater than the second data rate. 
     
     
         8 . The method of  claim 1 , wherein the first pads are coupled to an unbounded input/output (I/O) within the first die. 
     
     
         9 . The method of  claim 1 , wherein the first pads are wire-bond pads and the second pads are micro-bump pads. 
     
     
         10 . The method in  claim 1 , wherein the second die is of smaller size than the first die. 
     
     
         11 . The method of  claim 1  further comprising:
 disposing the first die on a package substrate, wherein the package substrate is in the package. 
 
     
     
         12 . The method of  claim 1 , wherein forming routings embedded below the surface of the first die further comprises:
 forming the routings such that each of the routings is the only electrical connection between one of the first pads and one of the second pads.   
     
     
         13 . The method of  claim 1 , wherein forming routings embedded below the surface of the first die further comprises:
 forming the routings only below the surface of the first die.   
     
     
         14 . A multiple-access memory system comprising:
 a first die comprising first and second pads on a surface of the first die, wherein the first die further comprises routings embedded below the surface of the first die, and wherein each of the routings connects one of the first pads to one of the second pads;   a second die stacked above the first die; and   interconnections that each couple the second die to the first die by physically contacting the second die and one of the second pads, wherein the first die and the second die are in a package, and wherein the first die is coupled to the second die via the first pads, the routings, the second pads, and the interconnections.   
     
     
         15 . The multiple-access memory system of  claim 14  further comprising:
 an integrated circuit in an additional package that is coupled to the package. 
 
     
     
         16 . The multiple-access memory system of  claim 14 , wherein each of the routings is the only electrical connection between one of the first pads and one of the second pads. 
     
     
         17 . The multiple-access memory system of  claim 14 , wherein the routings are only formed below the surface of the first die. 
     
     
         18 . The multiple-access memory system of  claim 14  further comprising:
 a package substrate coupled to the first die, wherein the package substrate is in the package. 
 
     
     
         19 . The multiple-access memory system of  claim 14 , wherein the second die is a memory die, and wherein the first die is one of a programmable logic device or a microprocessor. 
     
     
         20 . The multiple-access memory system of  claim 14 , wherein the first pads are coupled to an unbounded input/output (I/O) within the first die.