Dynamic frequency boosting in integrated circuits

Abstract

The disclosure is directed to the design and manufacture of synchronous digital systems, such as integrated circuits (IC), to employ dynamic frequency boosting. The proposed technique overcomes limitations of conventional synchronous clock design by boosting operating clock frequency despite critical path time constraints and without violating the correct functionality. In accordance with an exemplary embodiment, ICs are configured to set the clock frequency during each state event by selecting a more optimum clock frequency, on a clock cycle basis, thus improving system performance in terms of throughput while maintaining the benefits and design approach of synchronous digital systems.

1 . (canceled) 
     
     
         2 . A circuit device including a synchronous digital system comprising:
 a combinational circuit of one or multiple pipeline stages defined by a plurality of circuit paths of varying path delays;   a clock scheduler connected to predefined nodes of a subset of the plurality of circuit paths to allow hardware logic in the clock scheduler to process detected changes in signal state values at the predefined nodes, and in response thereto, to generate a clock selection signal indicating when a change in any of the detected changes is associated with a more optimum clock rate of operation when propagated from a predefined node to one or more downstream intersection nodes; and   a clock manager to set, in response to the clock selection signal, the operating clock rate of the combinational circuit to an optimum clock rate from among a plurality of selectable clock rates, the setting of the optimum clock rate occurring in runtime before the end of the clock cycle of operation during which the signal state values are detected, where by the time the signal switch state value changes are propagated to the one or more downstream intersection nodes, the optimum clock rate is already set.   
     
     
         3 . The circuit device of  claim 2 , wherein a switching in signal state value refers only to the change itself and not being a 0-bit value or a I-bit value. 
     
     
         4 . The circuit device of  claim 3 , wherein the combinational circuit comprises a data pipeline comprised of a sequence of stages, with registers defining the data starting points at the beginning of each of the sequence of stages. 
     
     
         5 . The circuit device of  claim 4 , where the registers store the output values of a preceding stage generated during a preceding clock cycle of operation. 
     
     
         6 . The circuit device of  claim 2 , wherein each intersection node is defined by at least one multiplexer circuit that logically divides a given stage into one or more sub-stages, the clock scheduler determining what paths are actively propagated at what pipeline stages, to sense signal state values at predetermined intersection nodes and to use those signal state values for the generation of the clock selection signal. 
     
     
         7 . The circuit device of  claim 2 , wherein the varying delays of the plurality of circuit paths define associated worst-case path delays derived from slack timing analysis and configured to avoid negative slack and provide a minimum possible positive slack. 
     
     
         8 . The device of  claim 2 , wherein the clock scheduler is designed to execute a clock frequency switching policy created using an appropriate electronic design automation (EDA) tool, the switching policy being the result of path analysis employed by the tool on the combinational circuit to identify path propagation delays and on the basis in part thereof, identify the subset of the registers of selected circuit paths that will be fed to the clock scheduler. 
     
     
         9 . The circuit device of  claim 8 , wherein the EDA tool is at least one of a plug-in and a standalone software solution configured to:
 identify a netlist, which netlist comprises a list of components and instances defining the synchronous digital system as well as the intersection nodes between the various components; and   amend the netlist to add the functionalities associated with the clock scheduler generating clock selection signals.   
     
     
         10 . The circuit device of  claim 8 , wherein the EDA tool is a stand-alone software solution configured to generate a netlist, which netlist comprises a list of components and instances defining the combination circuit as well as the intersection nodes between the various components in the combinational circuit, as well as define the components associated with the hardware logic in the clock scheduler. 
     
     
         11 . The circuit device of  claim 2 , wherein for any given single pipeline operation that results in the setting of a change in clock rate, both the entire single pipeline operation and the change in clock rate occur within a single clock of cycle of operation. 
     
     
         12 . The circuit device of  claim 11 , wherein the change in clock rate occurring within a single clock cycle of operation occurs in a cycle of operation preceding the triggering of the new clock rate. 
     
     
         13 . A non-transitory computer program product configured to operate as an EDA tool to assist a circuit designer to design a circuit device, the circuit device having a synchronous digital system including:
 a combinational circuit of one or multiple pipeline stages defined by a plurality of circuit paths of varying path delays,   a clock scheduler connected to predefined nodes of a subset of the plurality of circuit paths to allow hardware logic in the clock scheduler that are correlated with worst-case propagation path timing analysis to process detected changes in signal state values at the predefined nodes, and in response thereto, to generate a clock selection signal indicating when a change in any of the detected changes is associated with a more optimum clock rate of operation when propagated from a predefined node to one or more downstream intersection nodes, and   a clock manager to set, in response to the clock selection signal, the operating clock rate of the combinational logic to an optimum clock rate from among a plurality of selectable clock rates, the setting of the optimum clock rate occurring in runtime before the end of the clock cycle of operation during which the signal state values are detected, where by the time the signal switch state value changes are propagated to the one or more downstream intersection nodes, the optimum clock rate is already set, the computer program product including instructions that cause the EDA tool to:
 identify a netlist, which netlist comprises a list of components and instances defining the synchronous digital system as well as interconnection nodes between the various components; and 
 amend the netlist to add the functionalities associated with the clock scheduler to facilitate selecting the clock selection signal, 
 wherein the worst-case path timing analysis are derived from slack timing analysis and configured to avoid negative slack and provide a minimum possible positive slack. 
   
     
     
         14 . A non-transitory computer program product configured to operate as an EDA tool to assist a circuit designer to design a circuit device, the circuit device having a synchronous digital system including:
 a combinational circuit of one or multiple pipeline stages defined by a plurality of circuit paths of varying path delays,   a clock scheduler connected to predefined nodes of a subset of the plurality of circuit paths to allow hardware logic in the clock scheduler that are correlated with worst-case propagation path timing analysis to process detected changes in signal state values at the predefined nodes, and in response thereto, to generate a clock selection signal indicating when a change in any of the detected changes is associated with a more optimum clock rate of operation when propagated from a predefined node to one or more downstream intersection nodes, and   a clock manager to set, in response to the clock selection signal, the operating clock rate of the combinational logic to an optimum clock rate from among a plurality of selectable clock rates, the setting of the optimum clock rate occurring in runtime before the end of the clock cycle of operation during which the signal state values are detected, where by the time the signal switch state value changes are propagated to the one or more downstream intersection nodes, the optimum clock rate is already set, the computer program product including instructions that cause the EDA tool to:
 generate a netlist, which netlist comprises a list of components and instances defining the combinational circuit as well as intersection nodes between the various components in the combinational circuit, as well as define the components associated with the clock scheduler, 
 wherein the worst-case path timing analysis are derived from slack timing analysis and configured to avoid negative slack and provide a minimum possible positive slack. 
   
     
     
         15 . A computer implemented method for use with an EDA tool that assists a circuit designer to design a circuit device having a synchronous digital system including:
 a combinational circuit of one or multiple pipeline stages defined by a plurality of circuit paths of varying path delays,   a clock scheduler connected to predefined nodes of a subset of the plurality of circuit paths to allow hardware logic in the clock scheduler that are correlated with worst-case propagation path timing analysis to process detected changes in signal state values at the predefined nodes, and in response thereto, to generate a clock selection signal indicating when a change in any of the detected changes is associated with a more optimum clock rate of operation when propagated from a predefined node to one or more downstream intersection nodes, and   a clock manager to set, in response to the clock selection signal, the operating clock rate of the combinational logic to an optimum clock rate from among a plurality of selectable clock rates, the setting of the optimum clock rate occurring in runtime before the end of the clock cycle of operation during which the signal state values are detected, where by the time the signal switch state value changes are propagated to the one or more downstream intersection nodes, the optimum clock rate is already set, the method of designing the circuit device comprising:
 identifying a previously created netlist, which netlist comprises a list of components and instances defining the synchronous digital system as well as intersection nodes between the various components; 
 performing path analysis on the combinational circuit to identify, in part, path propagation delays and intersection nodes of the circuit paths; 
 defining a clock frequency switching policy based on the results of the path analysis; 
 identifying, based on the path analysis, the subset of registers of selected circuit paths that will be fed those inputs to the clock scheduler; and 
 amending the netlist to add the functionalities associated with the clock scheduler to facilitate generating the clock selection signal. 
   
     
     
         16 . A computer implemented method for use with an EDA tool that assists a circuit designer to design a circuit device including:
 a synchronous digital system including a combinational circuit of one or multiple pipeline stages defined by a plurality of circuit paths of varying path delays,   a clock scheduler connected to predefined nodes of a subset of the plurality of circuit paths to allow hardware logic in the clock scheduler that are correlated with worst-case propagation path timing analysis to process detected changes in signal state values at the predefined nodes, and in response thereto, to generate a clock selection signal indicating when a change in any of the detected changes is associated with a more optimum clock rate of operation when propagated from a predefined node to one or more downstream intersection nodes, and   a clock manager to set, in response to the clock selection signal, the operating rate of the combinational circuit to an optimum clock rate from among a plurality of selectable clock rates, the setting of the optimum clock rate occurring in runtime before the end of the clock cycle of operation during which the signal state values are detected, where by the time the signal switch state value changes are propagated to the one or more downstream intersection nodes, the optimum clock rate is already set, the method of designing the circuit device comprising:   performing path analysis on the combinational circuit to identify, in part, path propagation delays and intersection nodes of the circuit paths;   identifying, based on the path analysis, the subset of registers of selected circuit paths that will be fed those inputs to the clock scheduler; and   generating a netlist, which netlist comprises a list of components and instances defining the combination circuit as well as intersection nodes between the various components in the combinational circuit, as well as define the components associated with the clock scheduler.