Via Rail Structure

Abstract

The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC design layout defining a semiconductor structure having a via rail extending lengthwise in a first direction and contacting a source contact extending lengthwise in a second direction perpendicular to the first direction. The method further includes identifying the via rail, the source contact, a drain contact being distanced away from the source contact, and a gate structure interposing the source and drain contacts using pattern recognition on the IC design layout. The method further includes determining a position, length, and width of a jog via to be added to the IC design layout. The method further includes adding the jog via having the pre-determined length and width to the IC design layout at the pre-determined position to provide a modified IC design layout and generating a tape-out for fabricating a modified mask.

What is claimed is: 
     
         1 . A method for fabricating an integrated circuit (IC) comprising:
 receiving an IC design layout defining a semiconductor structure having a via rail extending lengthwise in a first direction and contacting a source contact extending lengthwise in a second direction perpendicular to the first direction;   identifying the via rail, the source contact, a drain contact being distanced away from the source contact, and a gate structure interposing the source and drain contacts using pattern recognition on the IC design layout;   determining a position of a jog via to be added to the IC design layout according to a location of the gate structure;   determining a length of the jog via according to a location of a sidewall surface of the source contact;   determining a width of the jog via according to a distance between the jog via and the drain contact;   adding the jog via having the pre-determined length and width to the IC design layout at the pre-determined position to provide a modified IC design layout; and   generating a tape-out for fabricating a modified mask, the tape-out being generated according to the modified IC design layout and including the jog via.   
     
     
         2 . The method of  claim 1 , wherein the determining of the position of the jog via includes determining the position such that a first end surface of the jog via facing the first direction is vertically aligned with a center line of the gate structure. 
     
     
         3 . The method of  claim 1 , wherein the determining of the length of the jog via includes determining the length such that the jog via extends entirely across a width of the source contact along the first direction. 
     
     
         4 . The method of  claim 1 , wherein the determining of the width of the jog via includes determining the width such that a minimum distance between the jog via and the drain contact is greater than or about equal to a minimum distance between an end surface of the drain contact facing the second direction and an opposing sidewall surface of the via rail. 
     
     
         5 . The method of  claim 4 , wherein the determining of the width of the jog via includes determining the width such that a minimum spacing along the second direction between the end surface of the drain contact and a sidewall surface the jog via is equal to about 2 nm. 
     
     
         6 . The method of  claim 1 , further comprising:
 fabricating the modified mask according to the tape-out; and   fabricating a semiconductor structure using the modified mask.   
     
     
         7 . The method of  claim 1 , wherein the identifying of the via rail and the source contact includes identifying a location of electrical contact between the via rail and the source contact. 
     
     
         8 . The method of  claim 1 , wherein the source contact is a first source contact and the jog via is a first jog via, further comprising:
 identifying a second source contact contacting the via rail; and   adding a second jog via to the IC design layout extending from the via rail along the second direction and contacting the second source contact.   
     
     
         9 . The method of  claim 1 , wherein the determining of the length of the jog via includes determining the length such that a second end surface of the jog via facing opposite the first end surface is vertically aligned with a center line of another gate structure. 
     
     
         10 . The method of  claim 1 , wherein the determining of the length of the jog via includes determining the length such that a second end surface of the jog via facing opposite the first end surface is vertically aligned with the sidewall surface of the source contact. 
     
     
         11 . A method for fabricating an integrated circuit (IC) comprising:
 providing a semiconductor structure including a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, and a source feature and a drain feature on the active region and interposed by the gate structure;   forming a source contact on the source feature and a drain contact on the drain feature, the source and drain contacts extending lengthwise parallel to the gate structure in the second direction; and   forming, on the source contact, a via rail including a main portion extending lengthwise in the first direction and including a jog via extending from a sidewall surface of the main portion along the second direction, wherein a minimum distance between the jog via and the drain contact is greater than or about equal to a minimum distance between the sidewall surface of the main portion of the via rail and an opposing end surface of the drain contact.   
     
     
         12 . The method of  claim 11 , wherein the forming of the via rail includes forming the jog via such that the jog via extends entirely across a width of the source contact along the first direction. 
     
     
         13 . The method of  claim 11 , wherein the forming of the via rail includes forming the jog via such that a minimum spacing along the second direction between the end surface of the drain contact and a sidewall surface of the jog via is equal to about 2 nm. 
     
     
         14 . The method of  claim 11 , wherein the forming of the via rail includes forming the main portion and the jog via by a same deposition process. 
     
     
         15 . The method of  claim 11 , wherein the gate structure includes a center line along the second direction, wherein the forming of the via rail includes forming the jog via having an end surface facing the first direction and being vertically aligned with the center line. 
     
     
         16 . A device comprising:
 a semiconductor substrate;   an active region over the semiconductor substrate extending lengthwise in a first direction;   a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction;   a source feature and a drain feature on the active region and interposed by the gate structure;   a source contact on the source feature extending lengthwise parallel to the gate structure;   a drain contact on the drain feature, the drain contact having an end surface facing the second direction; and   a via rail over the substrate spaced from the active region, the via rail including:
 a main portion extending lengthwise in the first direction, the main portion having a sidewall surface facing opposite the end surface of the drain contact; and 
 a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact, wherein a minimum distance between the jog via and the drain contact is greater than or about equal to a minimum distance between the end surface of the drain contact and the sidewall surface of the main portion of the via rail, and wherein the jog via includes an end surface facing the first direction and being vertically aligned with a center line of the gate structure. 
   
     
     
         17 . The device of  claim 16 , wherein a minimum spacing along the second direction between the end surface of the drain contact and the sidewall surface of the jog via is equal to about 2 nm. 
     
     
         18 . The device of  claim 16 , wherein the jog via extends entirely across a width of the source contact along the first direction. 
     
     
         19 . The device of  claim 16 , wherein the jog via is a first jog via of a plurality of jog vias extending from the via rail, wherein the source contact is a first source contact of a plurality of source contacts, and wherein each jog via directly contacts a single source contact. 
     
     
         20 . The device of  claim 19 , wherein a first resistance of the device including the plurality of jog vias is less than a second resistance of an equivalent device without the plurality of jog vias.