Integrated semiconductor assemblies and methods of manufacturing the same

Abstract

Integrated semiconductor assemblies and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device assembly comprises a base substrate having a cavity and a perimeter region at least partially surrounding the cavity. The cavity is defined by sidewalls extending at least partially through the substrate. The assembly further comprises a first die attached to the base substrate at the cavity, and a second die over at least a portion of the first die and attached to the base substrate at the perimeter region. In some embodiments, the first and second dies can be electrically coupled to each other via circuitry of the substrate.

1 . A semiconductor device assembly comprising:
 a base substrate having a cavity and a perimeter region at least partially surrounding the cavity, wherein the cavity extends at least partially through the base substrate and has an opening width measured across opposing edges of the perimeter region;   a first device in the cavity and attached to the base substrate at the cavity; and   a second device over at least a portion of the first device, extending across the opposing edges of the perimeter region, and attached to the base substrate at the perimeter region, wherein the second device has a device width that is greater than the opening width of the cavity; and   wherein a top surface of the first device and a bottom surface of the second device are separated by a distance corresponding to an air channel for cooling the first and second devices via convection.   
     
     
         2 . (canceled) 
     
     
         3 . (canceled) 
     
     
         4 . The assembly of  claim 1 , wherein the base substrate includes a continuous outermost surface spanning along a lower surface of the cavity and an upper surface of the perimeter region. 
     
     
         5 . The assembly of  claim 1  wherein the perimeter region includes an upper surface and the cavity includes a lower surface separated from the upper surface by a first distance, and wherein the first device includes the top surface separated from the lower surface of the cavity by a second distance less than the first distance. 
     
     
         6 . The assembly of  claim 1  wherein the perimeter region completely surrounds the cavity. 
     
     
         7 . The assembly of  claim 1 , further comprising an encapsulant at least partially encapsulating the first device, wherein a top surface of the encapsulant is below the bottom surface of the second device. 
     
     
         8 . The assembly of  claim 1 , further comprising a third device attached to the second device, wherein the third device is over the first device and the second device. 
     
     
         9 . The assembly of  claim 1  wherein the portion of the first device is a first portion, the assembly further comprising a third device attached to the base substrate at the perimeter region and spaced apart from the second device, wherein the third device is over at least a second portion of the first device. 
     
     
         10 . The assembly of  claim 1  wherein the base substrate includes a first side and a second side opposite the first side, wherein the perimeter region is a first perimeter region and the cavity is a first cavity, and wherein the first cavity and the first perimeter region are at the first side of the base substrate, the assembly further comprising:
 a cavity at the second side of the substrate and extending at least partially through the substrate toward the first side of the substrate; and 
 a second perimeter region at least partially surrounding the second cavity. 
 
     
     
         11 . The assembly of  claim 10 , further comprising:
 a third device in the second cavity and attached to the base substrate at the second cavity.   
     
     
         12 . The assembly of  claim 11 , further comprising:
 a fourth device over the third device and attached to the base substrate at the second perimeter region.   
     
     
         13 . The assembly of  claim 1  wherein the first device includes a memory chip and the second device includes a processor chip. 
     
     
         14 . The assembly of  claim 13  wherein one or more peripheral portions of the top surface of the memory chip laterally extends past corresponding peripheral edges of the processor chip. 
     
     
         15 . The assembly of  claim 14  wherein:
 the processor chip and the memory chip comprise a die stack; 
 the processor chip is located at a top portion of the die stack for releasing heat generated by the processor chip upward; and 
 the one or more peripheral portions of the top surface of the memory chip is uncovered by the processor chip for reducing thermal effect between the processor chip and the memory chip. 
 
     
     
         16 . A stacked package system comprising:
 a substrate having a cavity region and a perimeter region at least partially peripheral to the cavity region, wherein the cavity region is defined by sidewalls extending at least partially through the substrate and separated by an opening width measured across opposing portions of the side walls;   a first device attached to the substrate and positioned between the sidewalls of the cavity region; and   a second device over the first device, extending across the opening width and over the opposing portions of the perimeter region, and attached to the base substrate at the perimeter region, wherein the second device has a device width that is greater than the opening width of the cavity; and   wherein a top surface of the first device and a bottom surface of the second device are separated by a distance corresponding to an air channel for cooling the first and second devices via convection.   
     
     
         17 . The system of  claim 16  wherein the cavity region includes a lower surface between the sidewalls, and wherein the first device is attached to the lower surface via a plurality of connectors. 
     
     
         18 . The system of  claim 16  wherein the second device includes a bottom side facing at least partially toward the substrate and a top side opposite the bottom side, and wherein the first device is attached to the second device at the bottom side. 
     
     
         19 . The system of  claim 16 , further comprising a third device attached to the substrate, wherein the third device is stacked on the top side of the second device. 
     
     
         20 . The system of  claim 16  wherein at least a portion of the first device extends into the cavity region of the substrate. 
     
     
         21 . The system of  claim 16 , further comprising a third device spaced apart from the first device and attached to the substrate at the cavity region. 
     
     
         22 . The system of  claim 16  wherein the second device attached to the base substrate at the perimeter region is a first portion, and wherein the second device includes a second portion attached to the first device between the sidewalls of the cavity region. 
     
     
         23 . A method of forming a semiconductor device assembly, the method comprising:
 providing a base substrate having a cavity and a perimeter region at least partially surrounding the cavity, wherein the cavity extends at least partially through the base substrate and has an opening width measured across opposing edges of the perimeter region;   mounting a first device in the cavity and attached to the base substrate at the cavity; and   mounting a second device over at least a portion of the first device, extending across the opposing edges of the perimeter region, and attached to the base substrate at the perimeter region, wherein the second device has a device width that is greater than the opening width of the cavity;   wherein a top surface of the first device and a bottom surface of the second device are separated by a distance corresponding to an air channel for cooling the first and second devices via convection.