US2021090906A1PendingUtilityA1
Semiconductor Device and Method
Assignee: TAIWAN SEMICONDUCTOR MFG CO LTDPriority: Apr 2, 2014Filed: Nov 16, 2020Published: Mar 25, 2021
Est. expiryApr 2, 2034(~7.7 yrs left)· nominal 20-yr term from priority
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Claims
Abstract
A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device comprising:
a substrate, the substrate comprising a first region, a second region, and a third region interposed between the first region and the second region; a first semiconductor die bonded to the first region of the substrate; a second semiconductor die bonded to the second region of the substrate; a protective cap extending along a top surface of the first semiconductor die, a top surface of the second semiconductor die, and a top surface of the third region of the substrate; and an encapsulant extending along sidewalls of the first semiconductor die, sidewalls of the second semiconductor die, and sidewalls of the protective cap.
2 . The semiconductor device of claim 1 , wherein a top surface of the protective cap is level with a top surface of the encapsulant.
3 . The semiconductor device of claim 1 , wherein the protective cap comprises a metallic material.
4 . The semiconductor device of claim 1 , wherein the substrate comprises a plurality of conductive through vias.
5 . The semiconductor device of claim 1 , wherein a sidewall of the encapsulant is coplanar with a sidewall of the substrate.
6 . The semiconductor device of claim 1 , wherein a portion of the encapsulant is disposed above the third region of the substrate.
7 . The semiconductor device of claim 1 , wherein a thickness of the protective cap is between about 500 Å and about 2000 Å.
8 . A semiconductor device comprising:
a substrate; an encapsulant over the substrate; a protective cap embedded in the encapsulant, a top surface of the protective cap being level with a top surface of the encapsulant; a first semiconductor die embedded in the encapsulant, the first semiconductor die being interposed between the protective cap and the substrate, the first semiconductor die being electrically coupled to the substrate; and a second semiconductor die embedded in the encapsulant adjacent to the first semiconductor die, the second semiconductor die being interposed between the protective cap and the substrate, the second semiconductor die being electrically coupled to the substrate.
9 . The semiconductor device of claim 8 , wherein the first semiconductor die is electrically coupled to the substrate using a plurality of first connectors.
10 . The semiconductor device of claim 9 , wherein the second semiconductor die is electrically coupled to the substrate using a plurality of second connectors.
11 . The semiconductor device of claim 8 , wherein a portion of the encapsulant is interposed between the first semiconductor die and the second semiconductor die.
12 . The semiconductor device of claim 8 , wherein the protective cap comprises a conductive material.
13 . The semiconductor device of claim 8 , wherein the encapsulant is in physical contact with a sidewall of the protective cap.
14 . The semiconductor device of claim 8 , wherein a sidewall of the encapsulant is coplanar with a sidewall of the substrate.
15 . A method comprising:
bonding a first semiconductor die to a first region of a substrate; bonding a second semiconductor die to a second region of the substrate; forming a protective cap over the first semiconductor die, the second semiconductor die, and a third region of the substrate, wherein the third region of the substrate is interposed between the first region of the substrate and the second region of the substrate; applying an encapsulant over the protective cap, the first semiconductor die and the second semiconductor die; and removing a portion of the encapsulant to expose the protective cap.
16 . The method of claim 15 , further comprising performing a singulation process on the substrate and the encapsulant, wherein a sidewall of the substrate and a sidewall of the encapsulant are formed by the singulation process, and wherein the sidewall of the substrate is coplanar with the sidewall of the encapsulant.
17 . The method of claim 15 , wherein removing the portion of the encapsulant comprises performing a planarization process on the encapsulant.
18 . The method of claim 15 , further comprising forming a plurality of conductive through vias in the substrate.
19 . The method of claim 15 , wherein a top surface of the protective cap is level with a top surface of the encapsulant.
20 . The method of claim 15 , further comprising bonding a plurality of connectors to the substrate, wherein the substrate is interposed between the plurality of connectors and the first semiconductor die.Join the waitlist — get patent alerts
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