Cascode compound switch slew rate control

Abstract

A high-voltage (HV) compound switch can include coupling circuitry to help provide better slew rate (dV/dt) control, such as to limit electromagnetic energy radiation during switching, which can cause undesirable EMI. Further, efficiency and on-state resistance can be improved by controllably forward-biasing the “normally on” JFET when the compound switch is in an “on” state. In such an on-state, the JFET temperature can be monitored, such as by monitoring the gate-source junction voltage or the gate current of the JFET. Such temperature information can be used for control or other purposes.

1 . Switching circuitry providing slew-rate control, the switching circuitry comprising:
 a slew-rate controlled cascade compound switch comprising:
 a normally-off low voltage transistor (LVT), including drain, source, and gate terminals; and 
 a normally-on cascade high voltage transistor (HVT), including drain, source, and gate terminals, in series with the LVT to form the compound switch; 
   a first gate driver circuit, including an input terminal coupled to receive an input signal and an output terminal coupled to the gate of the LVT; and   coupling circuitry, coupled between the gate driver output and the gate of the HVT to drive a drain-gate capacitance of the HVT to limit a slew rate of a switching signal across the compound switch by a drive current characteristic of the first gate driver circuit during at least one of a turn-on or a turn-off of the compound switch; and   wherein the coupling circuitry includes an offset voltage circuit coupled to the gate of the HVT to provide an offset voltage to inhibit gate-source conduction of the HVT in response to a signal at the gate driver output that biases the LVT on, wherein the coupling circuitry includes at least one p-n semiconductor junction providing the offset voltage.   
     
     
         2 . The apparatus of  claim 1 , in which the coupling circuitry includes at least one or a series of diodes providing the offset voltage. 
     
     
         3 . The apparatus of  claim 1 , in which the coupling circuitry comprises anti-parallel first and second diodes respectively coupled to the gate of the HVT. 
     
     
         4 . The apparatus of  claim 1 , in which the HVT is a JFET and in which the LVT is a MOSFET. 
     
     
         5 . The apparatus of  claim 1 , in which the coupling circuitry includes different first and second current paths coupled to the gate driver output, only one of which is active to provide charge to the gate of the HVT during one of a turn-on transition or a turn-off transition of the compound switch. 
     
     
         6 . The apparatus of  claim 1 , in which the coupling circuitry includes at least one diode, to couple the gate of the HVT to the gate driver output. 
     
     
         7 . A method of switching to control electrical conduction between first and second nodes separated by a cascode compound switch that includes a higher voltage transistor (HVT) in series with a lower voltage transistor (LVT), the method comprising:
 using a first gate driver circuit, driving the gate of the LVT; and   limiting a switching slew rate of one of the first and second nodes, using a diode for providing controlled coupling between the gates of the HVT and the LVT.   
     
     
         8 . The method of  claim 7 , wherein limiting the switching slew rate comprises charging or discharging a gate-drain capacitance of the HVT by a current limited by the gate driver circuit. 
     
     
         9 . The method of  claim 7 , comprising limiting the switching slew rate of one of the first and second nodes during only one of turn-on or turn-off switching transitions of the compound switch. 
     
     
         10 . The method of  claim 7 , comprising limiting the switching slew rate of one of the first and second nodes asymmetrically with respect to turn-on and turn-off transitions of the compound switch. 
     
     
         11 . The method of  claim 7 , comprising providing an offset voltage between gates of the LVT and the HVT to limit or inhibit gate-source conduction of the HVT in response to a gate driver signal that biases the LVT on. 
     
     
         12 . The method of  claim 7 , wherein a specified offset voltage or fraction of a gate current of the HVT is coupled to a gate of the LVT during the driving the gate of the LVT. 
     
     
         13 . The method of  claim 7 , comprising driving the gate of the HVT to a voltage that is more positive than a source voltage of the HVT. 
     
     
         14 . The method of  claim 7 , wherein the HVT comprises a SiC, GaN, or other wide-bandgap transistor. 
     
     
         15 . An apparatus for switching to control electrical conduction between first and second nodes separated by a cascade compound switch that includes a higher voltage transistor (HVT) in series with a lower voltage transistor (LVT), the apparatus comprising:
 means for, using a first gate driver circuit, driving the gate of the LVT; and   means for limiting a switching slew rate of one of the first and second nodes, for providing controlled coupling between the gates of the HVT and the LVT.   
     
     
         16 . The apparatus of  claim 15 , wherein the means for limiting the switching slew rate comprises means for charging or discharging a gate-drain capacitance of the HVT by a current limited by the gate driver circuit. 
     
     
         17 . The apparatus of  claim 15 , comprising means for limiting the switching slew rate of one of the first and second nodes during only one of turn-on or turn-off switching transitions of the compound switch. 
     
     
         18 . The apparatus of  claim 15 , comprising means for limiting the switching slew rate of one of the first and second nodes asymmetrically with respect to turn-on and turn-off transitions of the compound switch. 
     
     
         19 . The apparatus of  claim 15 , comprising means for providing an offset voltage between gates of the LVT and the HVT to limit or inhibit gate-source conduction of the HVT in response to a gate driver signal that biases the LVT on. 
     
     
         20 . The apparatus of  claim 15 , wherein a specified offset voltage or fraction of a gate current of the HVT is coupled to a gate of the LVT during the driving the gate of the LVT.