Methods for memory interface calibration

Abstract

Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

1 - 20 . (canceled) 
     
     
         21 . A method, comprising:
 performing a calibration test on two or more memory ranks, wherein a memory device comprises the two or more memory ranks, and wherein the calibration test involves a read test, a write test, or both;   determining, for the two or more memory ranks, a range of timing settings for operating a respective rank based at least in part on the calibration test;   determining a common timing setting that is among the range of timing settings; and   configuring memory interface circuitry using the common timing setting.   
     
     
         22 . The method of  claim 21 , wherein configuring the memory interface circuitry comprises configuring a memory controller of the memory interface circuitry, memory interface calibration circuitry of the memory interface circuitry, a memory interface circuit of the memory interface circuitry, or any combination thereof. 
     
     
         23 . The method of  claim 21 , wherein configuring the memory interface circuitry comprises configuring the memory interface circuitry to communicate with a processor to transmit data to the processor read from the memory device, to receive data from the processor for storage in the memory device, or both. 
     
     
         24 . The method of  claim 21 , comprising configuring the memory interface circuitry to communicate using a double data rate protocol. 
     
     
         25 . The method of  claim 21 , comprising calibrating a field programmable gate array based at least in part on results from the read test when the calibration test involves the read test. 
     
     
         26 . The method of  claim 21 , wherein performing the calibration test comprises performing a first calibration test and a second calibration test at different times. 
     
     
         27 . The method of  claim 26 , comprising sensing one or more test values as one or more test measurements during the first calibration test, wherein performing the calibration test comprises oversampling the one or more test measurements using a predetermined oversampling factor. 
     
     
         28 . The method of  claim 21 , wherein performing the calibration test on the two or more memory ranks comprises communicating with a memory module of the memory device, and wherein the memory module comprises the two or more memory ranks. 
     
     
         29 . The method of  claim 21 , wherein performing the calibration test on the two or more memory ranks comprises communicating with a first memory module and a second memory module of the memory device, wherein the first memory module comprises one or more of the two or more memory ranks and the second memory module comprises an additional one or more of the two or more memory ranks. 
     
     
         30 . The method of  claim 21 , comprising:
 configuring the memory interface circuitry to enable communication of data signals and data strobe signals to the two or more memory ranks; and   centering, using the common timing setting, the data strobe signals relative to the data signals.   
     
     
         31 . The method of  claim 21 , wherein:
 performing the calibration test on the two or more memory ranks comprises:
 performing, using the memory interface circuitry configured to facilitate data communication between a programmable logic circuit and the memory device, a first calibration test of a first memory rank of the two or more memory ranks; and 
 performing, using the memory interface circuitry, a second calibration test of a second memory rank of the two or more memory ranks, wherein the memory interface circuitry is configured to perform the second calibration test separately from the first calibration test; 
   determining, for the two or more memory ranks, the range of timing settings for operating the respective rank comprises:
 determining a first range of settings for operating the first memory rank based at least in part on the first calibration test; and 
 determining a second range of settings for operating the second memory rank based at least in part on the second calibration test; and 
   determining the common timing setting that is among the range of timing settings comprises determining the common timing setting that is among the first range of settings and the second range of settings, wherein the memory interface circuitry operates based at least in part on the common timing setting.   
     
     
         32 . A tangible, non-transitory computer-readable medium configured to store instructions executable by a processor of an electronic device that, when executed by the processor, cause the processor to:
 perform a read test on two or more memory ranks;   determine, for the two or more memory ranks, a range of timing settings for operating the respective rank based at least in part on the respective read test;   determine a common timing setting that is among the range of timing settings; and   configure memory interface circuitry using the common timing setting.   
     
     
         33 . The tangible, non-transitory computer-readable medium of  claim 32 , wherein the instructions comprise instructions executable by the processor that, when executed by the processor, cause the processor to:
 configure the memory interface circuitry in such a way that it communicates data and data strobe signals to the two or more memory ranks; and   center, using the common timing setting, the data strobe signals relative to the data.   
     
     
         34 . The tangible, non-transitory computer-readable medium of  claim 32 , wherein the common timing setting comprises a delay setting. 
     
     
         35 . The tangible, non-transitory computer-readable medium of  claim 32 , wherein the common timing setting is centered within the range of timing settings. 
     
     
         36 . The tangible, non-transitory computer-readable medium of  claim 32 , wherein determining the range of timing settings comprises determining settings that enable the respective rank to successfully pass the read test. 
     
     
         37 . The tangible, non-transitory computer-readable medium of  claim 32 , wherein the instructions comprise instructions executable by the processor that, when executed by the processor, cause the processor to:
 perform the read test on the two or more memory ranks at least in part by:
 performing, using the memory interface circuitry configured to facilitate data communication between a programmable logic circuit of a field programmable gate array and multi-rank memory comprising the two or more memory ranks, a first read test of a first memory rank in the multi-rank memory; and 
 performing, using the memory interface circuitry, a second read test of a second memory rank in the multi-rank memory, wherein the memory interface circuitry is configured to perform the second read test separately from the first read test; 
   determine, for the two or more memory ranks, the range of timing settings for operating the respective rank at least in part by:
 determining a first range of timing settings for operating the first memory rank based at least in part on the first read test; and 
 determining a second range of timing settings for operating the second memory rank based at least in part on the second read test; 
   determine a common timing setting that is among the range of timing settings at least in part by determining a common setting that is among the first range of timing settings and the second range of timing settings; and   operate the memory interface circuitry using the common timing setting.   
     
     
         38 . A method for calibrating a field programmable gate array, comprising:
 performing, using memory interface circuitry configured to facilitate data communication between a programmable logic circuit of the field programmable gate array and multi-rank memory, a first calibration test of a first memory rank in the multi-rank memory;   performing, using the memory interface circuitry, a second calibration test of a second memory rank in the multi-rank memory, wherein the memory interface circuitry is configured to perform the second calibration test separately from the first calibration test;   determining a first range of settings for operating the first memory rank based at least in part on the first calibration test;   determining a second range of settings for operating the second memory rank based at least in part on the second calibration test;   determining a common setting that is among the first range of settings and the second range of settings; and   operating the memory interface circuitry using the common setting.   
     
     
         39 . The method of  claim 38 , wherein the first calibration test comprises a read calibration test, a write calibration test, or a combination thereof, and wherein determining the first range of settings comprises determining settings that enable the first memory rank to successfully pass the read calibration test, the write calibration test, or the combination thereof. 
     
     
         40 . The method of  claim 38 , wherein operating the memory interface circuitry using the common setting comprises using the memory interface circuitry to load data into the multi-rank memory.