Delay line, a delay locked loop circuit and a semiconductor apparatus using the delay line and the delay locked loop circuit

Abstract

A delay line includes a first delay cell and a second delay cell. The first delay cell inverts an input signal to generate a first output signal. The second delay cell inverts the first output signal to generate a second output signal. The driving forces of the first delay cell is adjusted on the basis of a delay control voltage and the second output signal.

What is claimed is: 
     
         1 . A delay line comprising:
 a first delay cell configured to invert an input signal to generate a first output signal; and   a second delay cell configured to invert the first output signal to generate a second output signal,   wherein pull-down driving force, with which the first delay cell pulls down the first output signal, is adjusted on the basis of a delay control voltage and the second output signal.   
     
     
         2 . The delay line of  claim 1 , wherein the first delay cell includes:
 a first inverter coupled between a node, from which a high voltage is provided, and a node, from which a low voltage is provided, and configured to invert the input signal to output a first output signal, the low voltage having a lower voltage level than the high voltage;   a first current source configured to adjust current flowing from the first inverter to the node, from which the low voltage is provided, based on the delay control voltage; and   a first feedback current source configured to further adjust the current flowing from the first inverter to the node, from which the low voltage is provided, based on the second output signal.   
     
     
         3 . The delay line of  claim 2 , wherein the first feedback current source further receives a first switching signal and is selectively coupled to the first inverter based on the first switching signal. 
     
     
         4 . The delay line of  claim 2 , further comprising a first auxiliary current source configured to further adjust the current flowing from the first inverter to the node, from which the low voltage is provided, based on the delay control voltage. 
     
     
         5 . The delay line of  claim 4 , wherein the first auxiliary current source further receives a second switching signal and is selectively coupled to the first inverter based on the second switching signal. 
     
     
         6 . The delay line of  claim 1 , wherein pull-down driving force, with which the second delay cell pulls down the second output signal, is adjusted on the basis of the delay control voltage and an output signal output from a subsequent delay cell, which is disposed subsequently to the second delay cell and configured to receive the second output signal. 
     
     
         7 . The delay line of  claim 6 , wherein the second delay cell includes:
 a second inverter coupled between a node, from which a high voltage is provided, and a node, from which a low voltage is provided, and configured to invert the first output signal to output a second output signal, the low voltage having a lower level than the high voltage;   a second current source configured to adjust current flowing from the second inverter to the node, from which the low voltage is provided, based on the delay control voltage; and   a second feedback current source configured to further adjust the current flowing from the second inverter to the node, from which the low voltage is provided, based on the output signal from the subsequent delay cell.   
     
     
         8 . The delay line of  claim 7 , wherein the second feedback current source further receives a first switching signal and is selectively coupled to the second inverter based on the first switching signal. 
     
     
         9 . The delay line of  claim 7 , further comprising a second auxiliary current source configured to further adjust the current flowing from the second inverter to the node, from which the low voltage is provided, based on the delay control voltage. 
     
     
         10 . The delay line of  claim 9 , wherein the second auxiliary current source further receives a second switching signal and is selectively coupled to the second inverter based on the second switching signal. 
     
     
         11 . A delay line comprising:
 a first delay cell configured to invert an input signal to generate a first output signal; and   a second delay cell configured to invert the first output signal to generate a second output signal,   wherein pull-up driving force, with which the first delay cell pulls up the first output signal, is adjusted on the basis of a delay control voltage and the second output signal.   
     
     
         12 . The delay line of  claim 11 , wherein the first delay cell includes:
 a first inverter coupled between a node, from which a high voltage is provided, and a node, from which a low voltage is provided, and configured to invert the input signal to output a first output signal, the low voltage having a lower level than the high voltage;   a first current source configured to adjust current flowing from the node, from which the high voltage is provided, to the first inverter based on the delay control voltage; and   a first feedback current source configured to further adjust the current flowing from the node, from which the high voltage is provided, to the first inverter based on the second output signal.   
     
     
         13 . The delay line of  claim 12 , wherein the first feedback current source further receives a first switching signal and is selectively coupled to the first inverter based on the first switching signal. 
     
     
         14 . The delay line of  claim 12 , further comprising a first auxiliary current source configured to further adjust the current flowing from the node, from which the high voltage is provided, to the first inverter based on the delay control voltage. 
     
     
         15 . The delay line of  claim 14 , wherein the first auxiliary current source further receives a second switching signal and is selectively coupled to the first inverter based on the second switching signal. 
     
     
         16 . The delay line of  claim 11 , wherein pull-up driving force, with which the second delay cell pulls up the second output signal, is adjusted on the basis of the delay control voltage and an output signal output from a subsequent delay cell, which is disposed subsequently to the second delay cell and configured to receive the second output signal. 
     
     
         17 . The delay line of  claim 16 , wherein the second delay cell includes:
 a second inverter coupled between a node, from which a high voltage is provided, and a node, from which a low voltage is provided, and configured to invert the first output signal to output a second output signal, the low voltage having a lower level than the high voltage;   a second current source configured to adjust current flowing from the node, from which the high voltage is provided, to the second inverter based on the delay control voltage; and   a second feedback current source configured to further adjust the current flowing from the node, from which the high voltage is provided, to the second inverter based on the output signal from the subsequent delay cell.   
     
     
         18 . The delay line of  claim 17 , wherein the second feedback current source further receives a first switching signal and is selectively coupled to the second inverter based on the first switching signal. 
     
     
         19 . The delay line of  claim 17 , further comprising a second auxiliary current source configured to further adjust the current flowing from the node, from which the high voltage is provided, to the second inverter based on the delay control voltage. 
     
     
         20 . The delay line of  claim 19 , wherein the second auxiliary current source further receives a second switching signal and is selectively coupled to the second inverter based on the second switching signal. 
     
     
         21 . A delay line comprising:
 a first delay cell configured to invert an input signal to generate a first output signal; and   a second delay cell configured to invert the first output signal to generate a second output signal,   wherein pull-up driving force, with which the first delay cell pulls up the first output signal, is adjusted on the basis of a pull-up delay control voltage and the second output signal and pull-down driving force, with which the first delay cell pulls down the first output signal, is adjusted on the basis of a pull-down delay control voltage and the second output signal.   
     
     
         22 . The delay line of  claim 21 , wherein the first delay cell includes:
 a first inverter coupled between a node, from which a high voltage is provided, and a node, from which a low voltage is provided, and configured to invert the input signal to output a first output signal, the low voltage having a lower level than the high voltage;   a first current source configured to adjust current flowing from the node, from which the high voltage is provided, to the first inverter based on the pull-up delay control voltage;   a second current source configured to adjust current flowing from the first inverter to the node, from which the low voltage is provided, based on the pull-down delay control voltage;   a first feedback current source configured to further adjust the current flowing from the node, from which the high voltage is provided, to the first inverter based on the second output signal; and   a second feedback current source configured to further adjust the current flowing from the first inverter to the node, from which the low voltage is provided, based on the second output signal.   
     
     
         23 . The delay line of  claim 22 , wherein each of the first feedback current source and the second feedback current source further receives a first switching signal and is selectively coupled to the first inverter based on the first switching signal. 
     
     
         24 . The delay line of  claim 22 , further comprising:
 a first auxiliary current source configured to further adjust the current flowing from the node, from which the high voltage is provided, to the first inverter based on the pull-up delay control voltage; and   a second auxiliary current source configured to further adjust the current flowing from the first inverter to the node, from which the low voltage is provided, based on the pull-down delay control voltage.   
     
     
         25 . The delay line of  claim 24 , wherein each of the first auxiliary current source and the second auxiliary current source further receives a second switching signal and is selectively coupled to the first inverter based on the second switching signal. 
     
     
         26 . The delay line of  claim 21 , wherein pull-up driving force, with which the second delay cell pulls up the second output signal, is adjusted on the basis of the pull-up delay control voltage and an output signal output from a subsequent delay cell, which is disposed subsequently to the second delay cell and configured to receive the second output signal, and pull-down driving force, with which the second delay cell pulls down the second output signal, is adjusted on the basis of the pull-down delay control voltage and the output signal output from the subsequent delay cell. 
     
     
         27 . The delay line of  claim 26 , wherein the second delay cell includes:
 a second inverter coupled between a node, from which a high voltage is provided, and a node, from which a low voltage is provided, and configured to invert the first output signal to output a second output signal, the low voltage having a lower level than the high voltage;   a third current source configured to adjust current flowing from the node, from which the high voltage is provided, to the second inverter based on the pull-up delay control voltage;   a fourth current source configured to adjust current flowing from the second inverter to the node, from which the low voltage is provided, based on the pull-down delay control voltage;   a third feedback current source configured to further adjust the current flowing from the node, from which the high voltage is provided, to the second inverter based on the output signal from the subsequent delay cell; and   a fourth feedback current source configured to further adjust the current flowing from the second inverter to the node, from which the low voltage is provided, based on the output signal from the subsequent delay cell.   
     
     
         28 . The delay line of  claim 27 , wherein each of the third feedback current source and the fourth feedback current source further receives a first switching signal and is selectively coupled to the second inverter based on the first switching signal. 
     
     
         29 . The delay line of  claim 27 , further comprising:
 a third auxiliary current source configured to further adjust the current flowing from the node, from which the high voltage is provided, to the second inverter based on the pull-up delay control voltage; and   a fourth auxiliary current source configured to further adjust the current flowing from the second inverter to the node, from which the low voltage is provided, based on the pull-down delay control voltage.   
     
     
         30 . The delay line of  claim 29 , wherein each of the third auxiliary current source and the fourth auxiliary current source further receives a second switching signal and is selectively coupled to the second inverter based on the second switching signal.