US2021074833A1PendingUtilityA1

Semiconductor device and method for manufacturing the same

Assignee: SEMICONDUCTOR ENERGY LABPriority: Mar 5, 2009Filed: Jun 15, 2020Published: Mar 11, 2021
Est. expiryMar 5, 2029(~2.6 yrs left)· nominal 20-yr term from priority
Inventors:Hajime Kimura
H10D 30/6755H10D 30/6723H10D 30/6739H10D 64/62H10D 86/441H10D 86/0231H10D 86/60H10D 86/40H10D 86/423H10D 62/80H10D 30/6743H10D 30/6737H10D 99/00H01L 29/7869H01L 27/124H01L 29/66969H01L 29/4908H01L 27/1288H01L 29/458H01L 29/26H01L 27/1214H01L 29/78633H01L 27/1225
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Claims

Abstract

A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.

Claims

exact text as granted — not AI-modified
1 . (canceled) 
     
     
         2 . A display device comprising:
 a first pixel comprising:
 a first transistor comprising a first oxide semiconductor layer; 
 a second transistor comprising a second oxide semiconductor layer; and 
 a pixel electrode; 
   a second pixel;   a first gate wiring electrically connected to the first pixel;   a source wiring electrically connected to the first pixel;   a power supply wiring electrically connected to the first pixel; and   a second gate wiring electrically connected to the second pixel,   wherein the first gate wiring is electrically connected to a gate of the first transistor,   wherein one of a source and a drain of the first transistor is electrically connected to the source wiring,   wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,   wherein one of a source and a drain of the second transistor is electrically connected to the power supply wiring,   wherein the other of the source and the drain of the second transistor is electrically connected to the pixel electrode,   wherein in a plan view, each of the first oxide semiconductor layer and the second oxide semiconductor layer is positioned in a region surrounded by the first gate wiring, the second gate wiring, the source wiring and the power supply wiring, and   wherein the pixel electrode overlaps the source wiring and the second gate wiring.   
     
     
         3 . The display device according to  claim 2 ,
 wherein the second pixel comprises a third transistor,   wherein one of a source and a drain of the third transistor is electrically connected to the source wiring, and   wherein the second gate wiring is electrically connected to a gate of the third transistor.   
     
     
         4 . The display device according to  claim 2 ,
 wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc.   
     
     
         5 . A display device comprising:
 a first pixel comprising:
 a first transistor comprising a first oxide semiconductor layer; 
 a second transistor comprising a second oxide semiconductor layer; and 
 a pixel electrode; 
   a second pixel;   a first gate wiring electrically connected to the first pixel;   a source wiring electrically connected to the first pixel;   a power supply wiring electrically connected to the first pixel; and   a second gate wiring electrically connected to the second pixel,   wherein the first gate wiring is electrically connected to a gate of the first transistor,   wherein one of a source and a drain of the first transistor is electrically connected to the source wiring,   wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,   wherein one of a source and a drain of the second transistor is electrically connected to the power supply wiring,   wherein the other of the source and the drain of the second transistor is electrically connected to the pixel electrode,   wherein in a plan view, each of the first oxide semiconductor layer and the second oxide semiconductor layer is positioned in a region surrounded by the first gate wiring, the second gate wiring, the source wiring and the power supply wiring, and   wherein the pixel electrode overlaps the first gate wiring, the source wiring, the power supply wiring and the second gate wiring.   
     
     
         6 . The display device according to  claim 5 ,
 wherein the second pixel comprises a third transistor,   wherein one of a source and a drain of the third transistor is electrically connected to the source wiring, and   wherein the second gate wiring is electrically connected to a gate of the third transistor.   
     
     
         7 . The display device according to  claim 5 ,
 wherein the pixel electrode comprises a first region having a first width and a second region having a second width,   wherein the first width is larger than the second width,   wherein the first region of the pixel electrode overlaps the source wiring and the power supply wiring, and   wherein the second region of the pixel electrode overlaps the first gate wiring.   
     
     
         8 . The display device according to  claim 5 ,
 wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc.

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