Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device in which the generation of a distortion of a signal is suppressed, and a method for manufacturing the semiconductor device, are disclosed. The semiconductor device includes a transistor region in which a field effect transistor is provided; and an interconnection region in which a metal layer electrically connected to the field effect transistor is provided. The interconnection region includes an insulating layer provided between the metal layer and a substrate, and a low-permittivity layer provided in the insulating layer below the metal layer and having a lower permittivity than the insulating layer.

1 . A semiconductor device comprising:
 a transistor region including a field effect transistor; and   an interconnection region including a metal layer electrically connected to the field effect transistor, wherein,   the interconnection region includes:
 an insulating layer provided between the metal layer and a substrate, and 
 a low-permittivity layer provided in the insulating layer below the metal layer and having a lower permittivity than the insulating layer wherein the low-permittivity layer is provided to pierce up to the substrate. 
   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising a plurality of low-permittivity layers arranged in a striped fashion. 
     
     
         3 . The semiconductor device according to  claim 1 , further comprising a plurality of low-permittivity layers arranged in a zigzag fashion. 
     
     
         4 . The semiconductor device according to  claim 1 , further comprising a plurality of insulating layers and a plurality of low-permittivity layers, wherein a low-permittivity layer of the plurality of low-permittivity layers is provided in each insulating layer of the plurality of insulating layers. 
     
     
         5 . The semiconductor device according to  claim 4 , wherein the low-permittivity layers of the plurality of low-permittivity layers do not overlap in a planar view of the substrate. 
     
     
         6 . The semiconductor device according to  claim 5 , wherein the low-permittivity layers of the plurality of low-permittivity layers are arranged in a zigzag fashion in a planar view of the substrate. 
     
     
         7 . (canceled) 
     
     
         8 . The semiconductor device according to  claim 1 , further comprising:
 an upper-side metal layer provided on the metal layer via an inter-metal insulating layer; and   an inter-metal low-permittivity layer having a lower permittivity than the inter-metal insulating layer provided in the inter-metal insulating layer between the metal layer and the upper-side metal layer.   
     
     
         9 . The semiconductor device according to  claim 1 , wherein the low-permittivity layer is provided in a projection region of the metal layer in a planar view of the substrate. 
     
     
         10 . The semiconductor device according to  claim 1 , wherein the metal layer is one of an interconnection and an electrode electrically connected to the field effect transistor. 
     
     
         11 . The semiconductor device according to  claim 1 , further comprising a plurality of low-permittivity layers, wherein
 at least either of upper ends and lower ends of the low-permittivity layers of the plurality of low-permittivity layers are provided in a same layer.   
     
     
         12 . The semiconductor device according to  claim 1 , wherein the field effect transistor is a field effect transistor for a radio frequency device. 
     
     
         13 . A method for manufacturing a semiconductor device, the method comprising:
 forming a field effect transistor in a transistor region; and   forming an interconnection region including a metal layer electrically connected to the field effect transistor, wherein the interconnection region includes:   an insulating layer provided between the metal layer and a substrate, and   a low-permittivity layer provided in the insulating layer below the metal layer and having a lower permittivity than the insulating layer, wherein the low-permittivity layer is provided to pierce up to the substrate.   
     
     
         14 . The method according to  claim 13 , further comprising forming a plurality of low-permittivity layers arranged in a striped fashion. 
     
     
         15 . The method according to  claim 13 , further comprising forming a plurality of low-permittivity layers arranged in a zigzag fashion. 
     
     
         16 . The method according to  claim 13 , further comprising forming a plurality of insulating layers and a plurality of low-permittivity layers, wherein a low-permittivity layer of the plurality of low-permittivity layers is provided in each insulating layer of the plurality of insulating layers. 
     
     
         17 . The method according to  claim 16 , wherein the low-permittivity layers of the plurality of low-permittivity layers do not overlap in a planar view of the substrate. 
     
     
         18 . The method according to  claim 17 , wherein the low-permittivity layers of the plurality of low-permittivity layers are arranged in a zigzag fashion in a planar view of the substrate. 
     
     
         19 . The method according to  claim 13 , further comprising:
 forming an upper-side metal layer provided on the metal layer via an inter-metal insulating layer; and   forming an inter-metal low-permittivity layer having a lower permittivity than the inter-metal insulating layer in the inter-metal insulating layer between the metal layer and the upper-side metal layer.   
     
     
         20 . The method according to  claim 13 , wherein the low-permittivity layer is provided in a projection region of the metal layer in a planar view of the substrate.