US2021066068A1PendingUtilityA1
Semiconductor wafer, manufacturing method for semiconductor wafer, and manufacturing method for semiconductor device
Est. expirySep 4, 2039(~13.1 yrs left)· nominal 20-yr term from priority
H10W 42/121H10P 90/18H10P 72/7614H10P 76/2041H10P 72/0616H10P 72/0421H10P 72/0402H10D 62/10H10D 62/117H01L 23/562H01L 21/02035
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Claims
Abstract
A semiconductor wafer according to an embodiment includes a support region facing a support member, an outer circumferential region positioned on an outer side of the support region, and an inner circumferential region positioned on an inner side of the support region. The outer circumferential region has a convex portion with a thickness protruded upward with respect to the inner circumferential region or a concave portion with a thickness recessed downward with respect to the inner circumferential region.
Claims
exact text as granted — not AI-modified1 . A semiconductor wafer comprising:
a support region facing a support member; an outer circumferential region positioned on an outer side of the support region; and an inner circumferential region positioned on an inner side of the support region, wherein the outer circumferential region has a convex portion with a thickness protruded upward with respect to the inner circumferential region or a concave portion with a thickness recessed downward with respect to the inner circumferential region.
2 . The semiconductor wafer of claim 1 , wherein
the support region has a shape of double rings, the wafer further comprises an intermediate region sandwiched by the support region, and the convex portion or the concave portion is provided on the intermediate region instead of the outer circumferential region.
3 . The semiconductor wafer of claim 1 , wherein the convex portion has a thickness larger than that of the inner circumferential region by a thickness not smaller than 10 nm and not larger than 10 μm.
4 . The semiconductor wafer of claim 1 , wherein the outer circumferential region is a region on an outer side than 0.9R where a radius of the semiconductor wafer is R.
5 . A manufacturing method for a semiconductor wafer comprising a support region facing a support member, an outer circumferential region positioned on an outer side of the support region, and an inner circumferential region positioned on an inner side of the support region, the method comprising
forming a convex portion with a thickness protruded upward with respect to the inner circumferential region or a concave portion with a thickness recessed downward with respect to the inner circumferential region, on the outer circumferential region.
6 . A manufacturing method for a semiconductor device, the method comprising:
supporting a semiconductor wafer with a support member provided between an outer circumferential region and an inner circumferential region, the wafer comprising a convex portion with a thickness protruded upward with respect to the inner circumferential region or a concave portion with a thickness recessed downward with respect to the inner circumferential region, the convex portion or the concave portion being formed on the outer circumferential region; and processing one of surfaces of the semiconductor wafer supported by the support member.
7 . The manufacturing method of claim 6 , comprising performing exposure processing of the one surface of the semiconductor wafer, with the one surface divided into a plurality of exposure pattern regions.
8 . The manufacturing method of claim 6 , comprising ejecting a film forming gas or an etching gas toward the one surface of the semiconductor wafer in a state where plasma is generated above the one surface.
9 . The manufacturing method of claim 6 , wherein the support member has a shape of a ring continuously surrounding the inner circumferential region along a circumferential direction of the semiconductor wafer.
10 . The manufacturing method of claim 6 , wherein the support member has a shape of pins dotted to intermittently surround the inner circumferential region along a circumferential direction of the semiconductor wafer.Join the waitlist — get patent alerts
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