Chip-stack structure

Abstract

The present disclosure provides a manufacturing method of a die-stack structure including follow steps. A first wafer including a first die is provided, wherein the first die includes a first substrate material layer, a first interconnect structure, and a first pad, and the first interconnect structure and the first pad are formed on the first substrate material layer in order, and the first substrate material layer has a first contact conductor disposed therein. a first contact conductor is disposed in the first substrate material layer. A second wafer including a second die is provided, wherein the second die includes a second substrate material layer, a second interconnect structure, and a second pad, and the second interconnect structure and the second pad are formed on the second substrate material layer in order, and the second substrate material layer has a second contact conductor disposed therein. A portion of the first substrate material layer is removed to form a first substrate, wherein the first contact conductor is exposed to a surface of the first substrate away from the first interconnect structure. The second wafer is covered on the first substrate such that the first contact conductor is directly physically in contact with the second pad.

What is claimed is: 
     
         1 . A chip-stack structure, comprising:
 a first chip comprising:
 a first substrate having a first surface and a second surface opposite to the first surface; 
 a first interconnect structure located on the first surface of the first substrate; and 
 a first contact conductor located in the first substrate and exposed on the second surface of the first substrate; 
   a second chip located on the first chip and comprising:
 a second substrate; 
 a second interconnect structure located on the second substrate; and 
 a second pad located on the second interconnect structure; 
   a first dielectric layer located on the second surface of the first substrate; and   a redistribution layer is formed on the second chip,   wherein the first contact conductor is directly physically in contact with the second pad, the first contact conductor has a width A, the second pad has a width B, and 5≤B/A.   
     
     
         2 . The chip-stack structure of  claim 1 , further comprising a first pad located on the first interconnect structure. 
     
     
         3 . The chip-stack structure of  claim 2 , wherein the first contact conductor does not directly physically in contact with the first pad. 
     
     
         4 . The chip-stack structure of  claim 1 , further comprising a second contact conductor located in the second substrate and electrically connected with the redistribution layer. 
     
     
         5 . The chip-stack structure of  claim 1 , wherein the second contact conductor does not physically directly in contact with the second pad. 
     
     
         6 . The chip-stack structure of  claim 1 , further comprising a second dielectric layer located between the redistribution layer and the second chip. 
     
     
         7 . The chip-stack structure of  claim 6 , wherein the second contact conductor is exposed on the second dielectric layer. 
     
     
         8 . The chip-stack structure of  claim 2 , further comprising a carrier plate located below the first chip, and the carrier plate comprises a plurality of dies. 
     
     
         9 . The chip-stack structure of  claim 8 , wherein a thickness of the plurality of dies of the carrier plate is greater than a thickness of the first chip. 
     
     
         10 . The chip-stack structure of  claim 2 , further comprises a carrier plate which is a carrier chip, and the first pad of the first chip is connected to a pad of the carrier chip. 
     
     
         11 . The chip-stack structure of  claim 1 , wherein the first contact conductor is a through-silicon via. 
     
     
         12 . The chip-stack structure of  claim 1 , wherein the first contact conductor does not cover the second surface of the first substrate. 
     
     
         13 . The chip-stack structure of  claim 1 , wherein a top surface of the first dielectric layer is coplanar with a top surface of the first contact conductor. 
     
     
         14 . The chip-stack structure of  claim 1 , wherein a portion of the first dielectric layer is directly physically in contact with the second pad. 
     
     
         15 . A chip-stack structure, comprising:
 a first chip comprising:
 a first substrate having a first surface and a second surface opposite to the first surface; 
 a first interconnect structure located on the first surface of the first substrate; 
 a first pad located on the first interconnect structure; and 
 a first contact conductor located in the first substrate and exposed on the second surface of the first substrate; 
   a second chip located on the first chip and comprising:
 a second substrate; 
 a second interconnect structure located on the second substrate; 
 a second pad located on the second interconnect structure; and 
 a second contact conductor located in the second substrate; 
   a first dielectric layer located between first chip and second chip; and   a redistribution layer is formed on and electrically connected to the second contact conductor,   wherein the first contact conductor is directly physically in contact with the second pad, the first contact conductor has a width A, the second pad has a width B, and 5≤B/A.   
     
     
         16 . The chip-stack structure of  claim 15 , wherein the first contact conductor does not directly physically in contact with the first pad. 
     
     
         17 . The chip-stack structure of  claim 15 , wherein the second contact conductor does not physically directly in contact with the second pad. 
     
     
         18 . The chip-stack structure of  claim 15 , wherein the first contact conductor is a through-silicon via. 
     
     
         19 . The chip-stack structure of  claim 15 , further comprising a second dielectric layer located between the redistribution layer and the second chip. 
     
     
         20 . The chip-stack structure of  claim 19  wherein the second contact conductor is exposed on the second dielectric layer. 
     
     
         21 . The chip-stack structure of  claim 15 , further comprising a carrier plate located below the first chip, and the carrier plate comprises a plurality of dies. 
     
     
         22 . The chip-stack structure of  claim 21 , wherein a thickness of the plurality of dies of the carrier plate is greater than a thickness of the first chip. 
     
     
         23 . The chip-stack structure of  claim 15 , further comprises a carrier plate which is a carrier chip, and the first pad of the first chip is connected to a pad of the carrier chip. 
     
     
         24 . The chip-stack structure of  claim 15 , wherein the first contact conductor does not cover the second surface of the first substrate. 
     
     
         25 . The chip-stack structure of  claim 15 , wherein a top surface of the first dielectric layer is coplanar with a top surface of the first contact conductor. 
     
     
         26 . The chip-stack structure of  claim 15 , wherein a portion of the first dielectric layer is directly physically in contact with the second pad.