Nonvolatile memory apparatus, and read and write method of the nonvolatile memory apparatus

Abstract

A non-volatile memory apparatus includes a memory cell coupled between a global bit line and a global word line. A bit line control circuit configured to apply a bit line read bias voltage to the global bit line based on a read signal. A snap-back detection circuit coupled to the global word line, and configured to generate a data output signal and a current enable signal by detecting a snap-back of the memory cell. A word line control circuit configured to apply a word line read bias voltage to the global word line based on the read signal, and may increase an amount of a current flowing through the memory cell based on the current enable signal.

What is claimed is: 
     
         1 . A non-volatile memory apparatus comprising:
 a memory cell coupled between a global bit line and a global word line;   a bit line control circuit configured to apply a bit line read bias voltage to the global bit line based on a read signal;   a sensing circuit configured to change a voltage level of a sensing node based on a voltage level of the global word line;   a current enable signal generation circuit configured to generate a current enable signal based on the voltage level of the sensing node; and   a word line control circuit configured to apply a word line read bias voltage to the global word line based on the read signal, and increase an amount of a current flowing through the memory cell based on the current enable signal.   
     
     
         2 . The non-volatile memory apparatus of  claim 1 ,
 wherein voltage level difference between the bit line read bias voltage and the word line read bias voltage corresponds to a voltage level of a read voltage, and   wherein the read voltage has a voltage level corresponding to a voltage between a set distribution maximum voltage and a reset distribution minimum voltage.   
     
     
         3 . The non-volatile memory apparatus of  claim 1 , further comprising:
 a data output circuit configured to generate the data output signal based on the voltage level of the sensing node and the read signal; and   an initialization circuit configured to initialize the voltage level of the sensing node and the current enable signal based on the read signal.   
     
     
         4 . The non-volatile memory apparatus of  claim 3 , further comprising a latch circuit configured to maintain, when the current enable signal is enabled, the enabled state of a voltage level of the current enable signal. 
     
     
         5 . The non-volatile memory apparatus of  claim 1 , wherein the word line control circuit includes:
 a snap-back current generation circuit configured to control a first current to flow through the global word line based on the read signal; and   an additional current generation circuit configured to control an additional current to flow through the global word line based on the current enable signal.   
     
     
         6 . The non-volatile memory apparatus of  claim 1 , wherein the word line control circuit includes:
 a first low voltage supply circuit configured to drive the global word line to a voltage level of the word line read bias voltage based on the read signal; and   a second low voltage supply circuit configured to drive the global word line to a voltage level of a first low voltage, which is lower than the word line read bias voltage, based on the current enable signal.   
     
     
         7 . A non-volatile memory apparatus comprising:
 a memory cell coupled between a global bit line and a global word line;   a bit line control circuit configured to apply a bit line read bias voltage to the global bit line based on a read signal;   a snap-back detection circuit coupled to the global word line, and configured to generate a data output signal and a current enable signal by detecting a snap-back of the memory cell; and   a word line control circuit configured to apply a word line read bias voltage to the global word line and to control a first current to flow through the global word line based on the read signal, and to control an additional current to flow through the global word line based on the current enable signal.   
     
     
         8 . The non-volatile memory apparatus of  claim 7 ,
 wherein voltage level difference between the bit line read bias voltage and the word line read bias voltage corresponds to a voltage level of a read voltage, and   wherein the read voltage has a voltage level corresponding to a voltage between a set distribution maximum voltage and a reset distribution minimum voltage.   
     
     
         9 . The non-volatile memory apparatus of  claim 7 ,
 wherein the snap-back detection circuit enables the current enable signal and the word line control circuit increases the amount of the current flowing through the memory cell, when a snap-back of the memory cell occurs, and   wherein the snap-back detection circuit disables the current enable signal when a snap-back of the memory cell does not occur.   
     
     
         10 . The non-volatile memory apparatus of  claim 7 , wherein the snap-back detection circuit includes:
 a sensing circuit configured to change a voltage level of a sensing node based on a voltage level of the global word line;   a data output circuit configured to generate the data output signal based on the voltage level of the sensing node and the read signal; and   a current enable signal generation circuit configured to generate the current enable signal based on the voltage level of the sensing node.   
     
     
         11 . The non-volatile memory apparatus of  claim 10 , further comprising an initialization circuit configured to initialize the voltage level of the sensing node and the current enable signal based on the read signal; and
 a latch circuit configured to maintain, when the current enable signal is enabled, the enabled state of a voltage level of the current enable signal.   
     
     
         12 . A write method of a non-volatile memory apparatus, the write method comprising:
 applying a write voltage, which is for causing a snap-back in a memory cell of a low resistance state or a memory cell of a high resistance state, across a memory cell coupled between a global bit line and a global word line; and   increasing an amount of a current flowing through the memory cell by an amount of a first current during a reset write operation, and increasing the amount of the current flowing through the memory cell by an amount of a second current, which is smaller than the first current, during a set write operation.   
     
     
         13 . The write method of  claim 12 , wherein the write voltage has a level equal to or greater than a reset distribution maximum voltage.